Extraction of accurate switched linear network models for high performance GaAs MESFET logic gates

Anthony E. Parker*, David J. Skellern

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

Abstract

Switched linear network models of MESFET logic circuits allow the investigation of large circuits with accuracy comparable to that obtained with device-level models in SPICE but with far less computational effort. The models achieve computational efficiency and accuracy through a scheme that switches between a small but sufficient number of networks of grounded linear elements which model all relevant regions of gate operation. The models are comparable and self-contained, so their interconnection inherently accounts for gate loading. Their structural basis permits automatic generation from a gate circuit description. A procedure for generating switched linear network models for a MESFET logic buffer stage is described. The simulation of a four-bit serial multiplier demonstrates the performance of the switched linear scheme and its excellent agreement with SPICE circuit simulation.

Original languageEnglish
Title of host publication12th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990
Subtitle of host publicationTechnical Digest
Place of PublicationPistacaway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages215-218
Number of pages4
DOIs
Publication statusPublished - Oct 1990
Event12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC - New Orleans, LA, USA
Duration: 7 Oct 199010 Oct 1990

Other

Other12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC
CityNew Orleans, LA, USA
Period7/10/9010/10/90

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