Extraction of accurate switched linear network models for high performance GaAs MESFET logic gates

Switched linear network models of MESFET logic circuits allow the investigation of large circuits with accuracy comparable to that obtained with device-level models in SPICE but with far less computational effort. The models achieve computational efficiency and accuracy through a scheme that switches between a small but sufficient number of networks of grounded linear elements which model all relevant regions of gate operation. The models are comparable and self-contained, so their interconnection inherently accounts for gate loading. Their structural basis permits automatic generation from a gate circuit description. A procedure for generating switched linear network models for a MESFET logic buffer stage is described. The simulation of a four-bit serial multiplier demonstrates the performance of the switched linear scheme and its excellent agreement with SPICE circuit simulation.