Fast, scalable, and highly accurate thermal modeling for use in GaN/GaAs RF circuit modeling platforms

A new steady-state thermal model for FETs has been developed which provides peak channel temperature estimates of individual gate fingers., something not available in off-the shelf RF-circuit simulation platforms. The model assists in simulating scaled transistor performance and aging quickly and accurately with demonstrated median error < 0.5 %. It provides designers with more flexibility as thermal resistance is automatically adjusted with power dissipation., base plate temperature., gate periphery., and gate-to-gate spacing., including non-uniform gate finger width and gate-to-gate spacing. The model was implemented into a customized Cadence®AWR simulation framework., allowing for seamless turn-key use by the RF circuit designer. The developed model was calibrated via 3D finite element method (FEM) simulations for the case of GaN on SiC HEMTs. However., it is fully upgradable and can be easily expanded to any gate-finger-based semiconductor technology where highly accurate and fast peak temperature modeling is needed., including GaAs., Si., SeGe., SiC., InP., etc. The model is also capable of handling different die substrate thicknesses and packaging substrates.