Framework for exploiting parallelism in chronolog

Chuchang Liu; Mehmet A. Orgun; Kang Zhang

doi:10.1109/ICAPP.1995.472181

Framework for exploiting parallelism in chronolog

Chuchang Liu^*, Mehmet A. Orgun, Kang Zhang

^*Corresponding author for this work

School of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

4 Citations (Scopus)

Abstract

Chronolog is an extension of logic programming based on temporal logic. The paper presents a framework which can be used to exploit multiple levels of parallelism found in Chronolog programs, context parallelism, AND- and OR-parallelism. Based on an analysis of these modes of parallelism in Chronolog programs occurs when more than one child-computation are active at a time, and it is exploited through dynamic tagging approach typically used in dataflow computers. At the level of clause arguments, we introduce an intermediate virtual machine (CVM), which is granulated to exploit the argument parallelism through temporal unification. We also give the details of the CVM instruction set. The model is process-based and supports AND-, OR-parallelism in the highly distributed dataflow environment.

Original language	English
Title of host publication	IEEE International Conference on Algorithms and Architectures for Parallel Processing
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	163-172
Number of pages	10
Volume	1
DOIs	https://doi.org/10.1109/ICAPP.1995.472181
Publication status	Published - 1995
Event	Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust Duration: 19 Apr 1995 → 21 Apr 1995

Other

Other	Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)
City	Brisbane, Aust
Period	19/04/95 → 21/04/95

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10.1109/ICAPP.1995.472181

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@inproceedings{71c731a8eb98413887f4cc02b8b95a63,

title = "Framework for exploiting parallelism in chronolog",

abstract = "Chronolog is an extension of logic programming based on temporal logic. The paper presents a framework which can be used to exploit multiple levels of parallelism found in Chronolog programs, context parallelism, AND- and OR-parallelism. Based on an analysis of these modes of parallelism in Chronolog programs occurs when more than one child-computation are active at a time, and it is exploited through dynamic tagging approach typically used in dataflow computers. At the level of clause arguments, we introduce an intermediate virtual machine (CVM), which is granulated to exploit the argument parallelism through temporal unification. We also give the details of the CVM instruction set. The model is process-based and supports AND-, OR-parallelism in the highly distributed dataflow environment.",

author = "Chuchang Liu and Orgun, {Mehmet A.} and Kang Zhang",

year = "1995",

doi = "10.1109/ICAPP.1995.472181",

language = "English",

volume = "1",

pages = "163--172",

booktitle = "IEEE International Conference on Algorithms and Architectures for Parallel Processing",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) ; Conference date: 19-04-1995 Through 21-04-1995",

}

Liu, C, Orgun, MA & Zhang, K 1995, Framework for exploiting parallelism in chronolog. in IEEE International Conference on Algorithms and Architectures for Parallel Processing. vol. 1, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 163-172, Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2), Brisbane, Aust, 19/04/95. https://doi.org/10.1109/ICAPP.1995.472181

Framework for exploiting parallelism in chronolog. / Liu, Chuchang; Orgun, Mehmet A.; Zhang, Kang.

IEEE International Conference on Algorithms and Architectures for Parallel Processing. Vol. 1 Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 1995. p. 163-172.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Liu, Chuchang

AU - Orgun, Mehmet A.

AU - Zhang, Kang

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N2 - Chronolog is an extension of logic programming based on temporal logic. The paper presents a framework which can be used to exploit multiple levels of parallelism found in Chronolog programs, context parallelism, AND- and OR-parallelism. Based on an analysis of these modes of parallelism in Chronolog programs occurs when more than one child-computation are active at a time, and it is exploited through dynamic tagging approach typically used in dataflow computers. At the level of clause arguments, we introduce an intermediate virtual machine (CVM), which is granulated to exploit the argument parallelism through temporal unification. We also give the details of the CVM instruction set. The model is process-based and supports AND-, OR-parallelism in the highly distributed dataflow environment.

AB - Chronolog is an extension of logic programming based on temporal logic. The paper presents a framework which can be used to exploit multiple levels of parallelism found in Chronolog programs, context parallelism, AND- and OR-parallelism. Based on an analysis of these modes of parallelism in Chronolog programs occurs when more than one child-computation are active at a time, and it is exploited through dynamic tagging approach typically used in dataflow computers. At the level of clause arguments, we introduce an intermediate virtual machine (CVM), which is granulated to exploit the argument parallelism through temporal unification. We also give the details of the CVM instruction set. The model is process-based and supports AND-, OR-parallelism in the highly distributed dataflow environment.

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DO - 10.1109/ICAPP.1995.472181

M3 - Conference proceeding contribution

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BT - IEEE International Conference on Algorithms and Architectures for Parallel Processing

PB - Institute of Electrical and Electronics Engineers (IEEE)

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T2 - Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)

Y2 - 19 April 1995 through 21 April 1995

ER -

Framework for exploiting parallelism in chronolog

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