Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

S. Kandeepan, S. Reisenfeld

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

4 Citations (Scopus)

Abstract

The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.

Original languageEnglish
Title of host publication8th international conference on communication systems, ICCS 2002 - proceedings
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages96-100
Number of pages5
ISBN (Electronic)0780375106, 9780780375109
ISBN (Print)0780375106
DOIs
Publication statusPublished - 2002
Externally publishedYes
Event8th International Conference on Communication Systems, ICCS 2002 - Singapore, Singapore
Duration: 25 Nov 200228 Nov 2002

Other

Other8th International Conference on Communication Systems, ICCS 2002
CountrySingapore
CitySingapore
Period25/11/0228/11/02

Keywords

  • Cramer-Rao bound (CRB)
  • Digital phase locked loop (DPLL)
  • modified Cramer-Rao bound
  • steady state frequency jitter
  • steady state phase jitter

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