Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

S. Kandeepan; S. Reisenfeld

doi:10.1109/ICCS.2002.1182445

Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

S. Kandeepan, S. Reisenfeld

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

4 Citations (Scopus)

Abstract

The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.

Original language	English
Title of host publication	8th international conference on communication systems, ICCS 2002 - proceedings
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	96-100
Number of pages	5
ISBN (Electronic)	0780375106, 9780780375109
ISBN (Print)	0780375106
DOIs	https://doi.org/10.1109/ICCS.2002.1182445
Publication status	Published - 2002
Externally published	Yes
Event	8th International Conference on Communication Systems, ICCS 2002 - Singapore, Singapore Duration: 25 Nov 2002 → 28 Nov 2002

Other

Other	8th International Conference on Communication Systems, ICCS 2002
Country/Territory	Singapore
City	Singapore
Period	25/11/02 → 28/11/02

Keywords

Cramer-Rao bound (CRB)
Digital phase locked loop (DPLL)
modified Cramer-Rao bound
steady state frequency jitter
steady state phase jitter

Access to Document

10.1109/ICCS.2002.1182445

Cite this

@inproceedings{59bfe8c469bb419a891d47e2688b9d89,

title = "Frequency jitter of a digital phase-locked loop and comparison with a modified CRB",

abstract = "The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.",

keywords = "Cramer-Rao bound (CRB), Digital phase locked loop (DPLL), modified Cramer-Rao bound, steady state frequency jitter, steady state phase jitter",

author = "S. Kandeepan and S. Reisenfeld",

year = "2002",

doi = "10.1109/ICCS.2002.1182445",

language = "English",

isbn = "0780375106 ",

pages = "96--100",

booktitle = "8th international conference on communication systems, ICCS 2002 - proceedings",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "8th International Conference on Communication Systems, ICCS 2002 ; Conference date: 25-11-2002 Through 28-11-2002",

}

Kandeepan, S & Reisenfeld, S 2002, Frequency jitter of a digital phase-locked loop and comparison with a modified CRB. in 8th international conference on communication systems, ICCS 2002 - proceedings., 1182445, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 96-100, 8th International Conference on Communication Systems, ICCS 2002, Singapore, Singapore, 25/11/02. https://doi.org/10.1109/ICCS.2002.1182445

Frequency jitter of a digital phase-locked loop and comparison with a modified CRB. / Kandeepan, S.; Reisenfeld, S.
8th international conference on communication systems, ICCS 2002 - proceedings. Piscataway, NJ: Institute of Electrical and Electronics Engineers (IEEE), 2002. p. 96-100 1182445.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

AU - Kandeepan, S.

AU - Reisenfeld, S.

PY - 2002

Y1 - 2002

N2 - The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.

AB - The steady state (SS) noise performance of a digital phase locked loop (DPLL) is of very much interest, while tracking carrier signals. In the literature the SS performance is very well examined in terms of the SS phase jitter, however the SS frequency jitter of a DPLL is unexamined up to now. In this paper we analyse the SS performance of a DPLL in terms of the frequency jitter. We derive a linearised expression for the SS frequency jitter of a DPLL, and verify it by simulations.

KW - Cramer-Rao bound (CRB)

KW - Digital phase locked loop (DPLL)

KW - modified Cramer-Rao bound

KW - steady state frequency jitter

KW - steady state phase jitter

UR - http://www.scopus.com/inward/record.url?scp=84961725702&partnerID=8YFLogxK

U2 - 10.1109/ICCS.2002.1182445

DO - 10.1109/ICCS.2002.1182445

M3 - Conference proceeding contribution

AN - SCOPUS:84961725702

SN - 0780375106

SP - 96

EP - 100

BT - 8th international conference on communication systems, ICCS 2002 - proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, NJ

T2 - 8th International Conference on Communication Systems, ICCS 2002

Y2 - 25 November 2002 through 28 November 2002

ER -

Frequency jitter of a digital phase-locked loop and comparison with a modified CRB

Abstract

Other

Keywords

Access to Document

Other files and links

Fingerprint

Cite this