From C to fault-tolerant FPGA-based systems

Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

1 Citation (Scopus)

Abstract

This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis (HLS) tool to generate triplicated register-transfer level designs for algorithms expressed in the C language and Vivado design suite for their implementation on Xilinx 7-series FPGAs. TLegUp has been extended to partition the design into a number of Triple Modular Redundant (TMR) components, which can be optionally floorplanned during their implementation. Partitioning the TMR design into a network of smaller TMR components and isolating their modules through flooplanning increases system reliability. We implemented a fine- and a coarse grain approach to partition the design, whereby the former approach uses a network flow algorithm to partition the application's Data Flow Graph (DFG) at the instruction level, while the latter uses the same algorithm to partition the design at the C function level. Results reveal that both approaches provide similar reliability enhancement to the system, but function-level partitioned designs are smaller and faster.
Original languageEnglish
Title of host publicationProceedings 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018)
Place of PublicationLos Alamitos
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages212
Number of pages1
ISBN (Electronic)9781538655221
DOIs
Publication statusPublished - 2018
Event26th IEEE International Symposium on Field-Programmable Custom
Computing Machines, FCCM 2018
- Boulder, United States
Duration: 29 Apr 20181 May 2018

Conference

Conference26th IEEE International Symposium on Field-Programmable Custom
Computing Machines, FCCM 2018
CountryUnited States
CityBoulder
Period29/04/181/05/18

Keywords

  • Field programmable gate arrays
  • Tunneling magnetoresistance
  • Partitioning algorithms
  • Tools
  • Hardware design languages
  • Clustering algorithms
  • Fault tolerance
  • FPGA
  • TMR
  • HLS
  • CAD
  • TLegUp
  • LegUp
  • Floorplanning
  • SEU
  • Soft errors
  • Space
  • Space Applications
  • Partitioning
  • SRAM based FPGA
  • Fault injection
  • Design Automation
  • SEU mitigation
  • Xilinx FPGA
  • Triple Modular Redundancy

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