From C to fault-tolerant FPGA-based systems

Dimitris Agiakatsikas; Ganghee Lee; Thomas Mitchell; Ediz Cetin; Oliver Diessel

doi:10.1109/FCCM.2018.00046

From C to fault-tolerant FPGA-based systems

Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

3 Citations (Scopus)

Abstract

This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis (HLS) tool to generate triplicated register-transfer level designs for algorithms expressed in the C language and Vivado design suite for their implementation on Xilinx 7-series FPGAs. TLegUp has been extended to partition the design into a number of Triple Modular Redundant (TMR) components, which can be optionally floorplanned during their implementation. Partitioning the TMR design into a network of smaller TMR components and isolating their modules through flooplanning increases system reliability. We implemented a fine- and a coarse grain approach to partition the design, whereby the former approach uses a network flow algorithm to partition the application's Data Flow Graph (DFG) at the instruction level, while the latter uses the same algorithm to partition the design at the C function level. Results reveal that both approaches provide similar reliability enhancement to the system, but function-level partitioned designs are smaller and faster.

Original language	English
Title of host publication	Proceedings 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018)
Place of Publication	Los Alamitos
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	212
Number of pages	1
ISBN (Electronic)	9781538655221
DOIs	https://doi.org/10.1109/FCCM.2018.00046
Publication status	Published - 2018
Event	26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018 - Boulder, United States Duration: 29 Apr 2018 → 1 May 2018

Conference

Conference	26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018
Country/Territory	United States
City	Boulder
Period	29/04/18 → 1/05/18

Keywords

Field programmable gate arrays
Tunneling magnetoresistance
Partitioning algorithms
Tools
Hardware design languages
Clustering algorithms
Fault tolerance
FPGA
TMR
HLS
CAD
TLegUp
LegUp
Floorplanning
SEU
Soft errors
Space
Space Applications
Partitioning
SRAM based FPGA
Fault injection
Design Automation
SEU mitigation
Xilinx FPGA
Triple Modular Redundancy

Access to Document

10.1109/FCCM.2018.00046

Cite this

@inproceedings{7c37d78dd4c2446ca54c13da58198388,

title = "From C to fault-tolerant FPGA-based systems",

abstract = "This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis (HLS) tool to generate triplicated register-transfer level designs for algorithms expressed in the C language and Vivado design suite for their implementation on Xilinx 7-series FPGAs. TLegUp has been extended to partition the design into a number of Triple Modular Redundant (TMR) components, which can be optionally floorplanned during their implementation. Partitioning the TMR design into a network of smaller TMR components and isolating their modules through flooplanning increases system reliability. We implemented a fine- and a coarse grain approach to partition the design, whereby the former approach uses a network flow algorithm to partition the application's Data Flow Graph (DFG) at the instruction level, while the latter uses the same algorithm to partition the design at the C function level. Results reveal that both approaches provide similar reliability enhancement to the system, but function-level partitioned designs are smaller and faster.",

keywords = "Field programmable gate arrays, Tunneling magnetoresistance, Partitioning algorithms, Tools, Hardware design languages, Clustering algorithms, Fault tolerance, FPGA, TMR, HLS, CAD, TLegUp, LegUp, Floorplanning, SEU, Soft errors, Space, Space Applications, Partitioning, SRAM based FPGA, Fault injection, Design Automation, SEU mitigation, Xilinx FPGA, Triple Modular Redundancy",

author = "Dimitris Agiakatsikas and Ganghee Lee and Thomas Mitchell and Ediz Cetin and Oliver Diessel",

year = "2018",

doi = "10.1109/FCCM.2018.00046",

language = "English",

pages = "212",

booktitle = "Proceedings 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018)",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "26th IEEE International Symposium on Field-Programmable Custom<br/>Computing Machines, FCCM 2018 ; Conference date: 29-04-2018 Through 01-05-2018",

}

Agiakatsikas, D, Lee, G, Mitchell, T, Cetin, E & Diessel, O 2018, From C to fault-tolerant FPGA-based systems. in Proceedings 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018). Institute of Electrical and Electronics Engineers (IEEE), Los Alamitos, pp. 212, 26th IEEE International Symposium on Field-Programmable Custom
Computing Machines, FCCM 2018, Boulder, Colorado, United States, 29/04/18. https://doi.org/10.1109/FCCM.2018.00046

From C to fault-tolerant FPGA-based systems. / Agiakatsikas, Dimitris; Lee, Ganghee; Mitchell, Thomas et al.
Proceedings 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018). Los Alamitos: Institute of Electrical and Electronics Engineers (IEEE), 2018. p. 212.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - From C to fault-tolerant FPGA-based systems

AU - Agiakatsikas, Dimitris

AU - Lee, Ganghee

AU - Mitchell, Thomas

AU - Cetin, Ediz

AU - Diessel, Oliver

PY - 2018

Y1 - 2018

N2 - This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis (HLS) tool to generate triplicated register-transfer level designs for algorithms expressed in the C language and Vivado design suite for their implementation on Xilinx 7-series FPGAs. TLegUp has been extended to partition the design into a number of Triple Modular Redundant (TMR) components, which can be optionally floorplanned during their implementation. Partitioning the TMR design into a network of smaller TMR components and isolating their modules through flooplanning increases system reliability. We implemented a fine- and a coarse grain approach to partition the design, whereby the former approach uses a network flow algorithm to partition the application's Data Flow Graph (DFG) at the instruction level, while the latter uses the same algorithm to partition the design at the C function level. Results reveal that both approaches provide similar reliability enhancement to the system, but function-level partitioned designs are smaller and faster.

AB - This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis (HLS) tool to generate triplicated register-transfer level designs for algorithms expressed in the C language and Vivado design suite for their implementation on Xilinx 7-series FPGAs. TLegUp has been extended to partition the design into a number of Triple Modular Redundant (TMR) components, which can be optionally floorplanned during their implementation. Partitioning the TMR design into a network of smaller TMR components and isolating their modules through flooplanning increases system reliability. We implemented a fine- and a coarse grain approach to partition the design, whereby the former approach uses a network flow algorithm to partition the application's Data Flow Graph (DFG) at the instruction level, while the latter uses the same algorithm to partition the design at the C function level. Results reveal that both approaches provide similar reliability enhancement to the system, but function-level partitioned designs are smaller and faster.

KW - Field programmable gate arrays

KW - Tunneling magnetoresistance

KW - Partitioning algorithms

KW - Tools

KW - Hardware design languages

KW - Clustering algorithms

KW - Fault tolerance

KW - FPGA

KW - TMR

KW - HLS

KW - CAD

KW - TLegUp

KW - LegUp

KW - Floorplanning

KW - SEU

KW - Soft errors

KW - Space

KW - Space Applications

KW - Partitioning

KW - SRAM based FPGA

KW - Fault injection

KW - Design Automation

KW - SEU mitigation

KW - Xilinx FPGA

KW - Triple Modular Redundancy

U2 - 10.1109/FCCM.2018.00046

DO - 10.1109/FCCM.2018.00046

M3 - Conference proceeding contribution

SP - 212

BT - Proceedings 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018)

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Los Alamitos

T2 - 26th IEEE International Symposium on Field-Programmable Custom<br/>Computing Machines, FCCM 2018

Y2 - 29 April 2018 through 1 May 2018

ER -

From C to fault-tolerant FPGA-based systems

Abstract

Conference

Keywords

Access to Document

Fingerprint

Cite this