Full chip power benefits with negative capacitance FETs

Sandeep K. Samal; Sourabh Khandelwal; Asif I. Khan; Sayeef Salahuddin; Chenming Hu; Sung Kyu Lim

doi:10.1109/ISLPED.2017.8009170

Full chip power benefits with negative capacitance FETs

Sandeep K. Samal, Sourabh Khandelwal, Asif I. Khan, Sayeef Salahuddin, Chenming Hu, Sung Kyu Lim

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

24 Citations (Scopus)

Abstract

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

Original language	English
Title of host publication	IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) 2017 : proceedings
Place of Publication	Piscataway, NJ, USA
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781509060238
ISBN (Print)	9781509060245
DOIs	https://doi.org/10.1109/ISLPED.2017.8009170
Publication status	Published - 11 Aug 2017
Event	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan Duration: 24 Jul 2017 → 26 Jul 2017

Conference

Conference	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Country/Territory	Taiwan
City	Taipei
Period	24/07/17 → 26/07/17

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10.1109/ISLPED.2017.8009170

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Samal, S. K., Khandelwal, S., Khan, A. I., Salahuddin, S., Hu, C., & Lim, S. K. (2017). Full chip power benefits with negative capacitance FETs. In IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) 2017 : proceedings (pp. 1-6). Article 8009170 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISLPED.2017.8009170

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title = "Full chip power benefits with negative capacitance FETs",

abstract = "We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7\%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.",

author = "Samal, \{Sandeep K.\} and Sourabh Khandelwal and Khan, \{Asif I.\} and Sayeef Salahuddin and Chenming Hu and Lim, \{Sung Kyu\}",

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Samal, SK, Khandelwal, S, Khan, AI, Salahuddin, S, Hu, C & Lim, SK 2017, Full chip power benefits with negative capacitance FETs. in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) 2017 : proceedings., 8009170, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, USA, pp. 1-6, 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, 24/07/17. https://doi.org/10.1109/ISLPED.2017.8009170

Full chip power benefits with negative capacitance FETs. / Samal, Sandeep K.; Khandelwal, Sourabh; Khan, Asif I. et al.
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) 2017 : proceedings. Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers (IEEE), 2017. p. 1-6 8009170.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Samal, Sandeep K.

AU - Khandelwal, Sourabh

AU - Khan, Asif I.

AU - Salahuddin, Sayeef

AU - Hu, Chenming

AU - Lim, Sung Kyu

PY - 2017/8/11

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N2 - We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

AB - We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

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ER -

Full chip power benefits with negative capacitance FETs

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