GaAs 600 Mbit/s 24B1P coder/decoder ASIC

Mark L. Parrilla; David J. Skellern; Simon J. Mahon; Terence M. Percival

GaAs 600 Mbit/s 24B1P coder/decoder ASIC

Mark L. Parrilla^*, David J. Skellern, Simon J. Mahon, Terence M. Percival

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented.

Original language	English
Title of host publication	Second Annual IEEE ASIC Seminar and Exhibit
Place of Publication	New York
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Publication status	Published - 1989
Externally published	Yes
Event	Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit - Rochester, NY, USA Duration: 25 Sept 1989 → 28 Sept 1989

Other

Other	Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit
City	Rochester, NY, USA
Period	25/09/89 → 28/09/89

Cite this

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title = "GaAs 600 Mbit/s 24B1P coder/decoder ASIC",

abstract = "The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented.",

author = "Parrilla, {Mark L.} and Skellern, {David J.} and Mahon, {Simon J.} and Percival, {Terence M.}",

year = "1989",

language = "English",

booktitle = "Second Annual IEEE ASIC Seminar and Exhibit",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit ; Conference date: 25-09-1989 Through 28-09-1989",

}

TY - GEN

T1 - GaAs 600 Mbit/s 24B1P coder/decoder ASIC

AU - Parrilla, Mark L.

AU - Skellern, David J.

AU - Mahon, Simon J.

AU - Percival, Terence M.

PY - 1989

Y1 - 1989

N2 - The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented.

AB - The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented.

UR - http://www.scopus.com/inward/record.url?scp=18344410454&partnerID=8YFLogxK

M3 - Conference proceeding contribution

AN - SCOPUS:18344410454

BT - Second Annual IEEE ASIC Seminar and Exhibit

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - New York

T2 - Proceedings of the Second Annual IEEE ASIC Seminar and Exhibit

Y2 - 25 September 1989 through 28 September 1989

ER -

GaAs 600 Mbit/s 24B1P coder/decoder ASIC

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