GaAs 600 Mbit/s 24B1P coder/decoder ASIC

Mark L. Parrilla*, David J. Skellern, Simon J. Mahon, Terence M. Percival

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

Abstract

The technical details, tradeoffs, and economics associated with the design of a gallium arsenide 600-Mb/s 24B1P coder/decoder ASIC (application-specific integrated circuit) are reviewed. Key features of the design include the use of common components to allow integration of encoder and decoder on the one chip, a novel data accelerator/decelerator, and the use of asynchronous control circuitry. The ASIC is evaluated in terms of both complexity and effort in relation to designing with gallium arsenide standard cells. An improved design that can operate at rates in excess of 1.3 Gb/s is presented.

Original languageEnglish
Title of host publicationSecond Annual IEEE ASIC Seminar and Exhibit
Place of PublicationNew York
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Publication statusPublished - 1989
Externally publishedYes
EventProceedings of the Second Annual IEEE ASIC Seminar and Exhibit - Rochester, NY, USA
Duration: 25 Sept 198928 Sept 1989

Other

OtherProceedings of the Second Annual IEEE ASIC Seminar and Exhibit
CityRochester, NY, USA
Period25/09/8928/09/89

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