High-performance and high-speed implementation of polynomial basis Itoh-Tsuji inversion algorithm over GF(2m)

Bahram Rashidi*, Reza Rezaeian Farashahi, Sayed Masoud Sayedi

*Corresponding author for this work

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

In this study high-performance and high-speed field-programmable gate array (FPGA) implementations of polynomial basis Itoh-Tsuji inversion algorithm (ITA) over GF(2m) constructed by irreducible trinomials and pentanomials are presented. The proposed structures are designed by one field multiplier and κ-times squarer blocks or exponentiation by 2κ, where κ is a small positive integer. The κ-times squarer blocks have an efficient tree structure with low critical path delay, and the multiplier is based on a proposed high-speed digit-serial architecture with minimum hardware resources. Furthermore, to reduce the computation time of ITA, the critical path of the circuit is broken to finer path using several registers. The computation times of the structure on Virtex-4 FPGA family are 0.262, 0.192 and 0.271 μs for GF(2163), GF(2193) and GF(2233), respectively. The comparison results with other implementations of the polynomial basis Itoh-Tsuji inversion algorithm verify the improvement in the proposed architecture in terms of speed and performance.

Original languageEnglish
Pages (from-to)66-77
Number of pages12
JournalIET Information Security
Volume11
Issue number2
DOIs
Publication statusPublished - 1 Mar 2017
Externally publishedYes

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