High-performance elliptic curve cryptography processor over NIST prime fields

Md Selim Hossain*, Yinan Kong, Ehsan Saeedi, Niras C. Vayalil

*Corresponding author for this work

Research output: Contribution to journalArticle

24 Citations (Scopus)


This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high-performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards and Technology standard. A novel combined point doubling and point addition architecture is proposed using efficient modular arithmetic to achieve high speed and low hardware utilisation of the ECP in Jacobian coordinates. This new architecture has been synthesised both in application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA). A 65 nm CMOS ASIC implementation of the proposed ECP in Jacobian coordinates takes between 0.56 and 0.73 ms for 224-bit and 256-bit elliptic curve cryptography, respectively. The ECSM is also implemented in an FPGA and provides a better delay performance than previous designs. The implemented design is area-efficient and this means that it requires not many resources, without any digital signal processing (DSP) slices, on an FPGA. Moreover, the area-delay product of this design is very low compared with similar designs. To the best of the authors' knowledge, the ECP proposed in this study over Fp performs better than available hardware in terms of area and timing.

Original languageEnglish
Pages (from-to)33-42
Number of pages10
JournalIET Computers and Digital Techniques
Issue number1
Publication statusPublished - 2017

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