High radix montgomery multipliers for residue arithmetic channels on FPGAs

Yinan Kong*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

1 Citation (Scopus)

Abstract

This work targets an efficient Montgomery Modular Multiplier for use in the channels of a Residue Number System (RNS). It is implemented on FPGA and optimized by attempting and evaluating the high radix techniques of the Montgomery Algorithm. The usual correction shift step at the end is proved to be infeasible. The resulting multiplier achieves 15ns for a modular multiplication using high radix without correction shift.

Original languageEnglish
Title of host publicationFuture Intelligent Information Systems
EditorsDehuai Zeng
Place of PublicationBerlin; Heidelberg
PublisherSpringer, Springer Nature
Pages23-30
Number of pages8
Volume86
ISBN (Electronic)9783642197062
ISBN (Print)9783642197055
DOIs
Publication statusPublished - 2011
Event2010 International Conference on Electrical and Electronics Engineering, ICEEE 2010 - Wuhan, China
Duration: 4 Dec 20105 Dec 2010

Publication series

NameLecture Notes in Electrical Engineering
NumberVOL. 1
Volume86 LNEE
ISSN (Print)18761100
ISSN (Electronic)18761119

Other

Other2010 International Conference on Electrical and Electronics Engineering, ICEEE 2010
CountryChina
CityWuhan
Period4/12/105/12/10

Keywords

  • Digital Arithmetic
  • FPGA
  • Montgomery Modular Multiplication
  • Public-Key Cryptosystems
  • the Residue Number System

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