High radix montgomery multipliers for residue arithmetic channels on FPGAs

Yinan Kong

doi:10.1007/978-3-642-19706-2_4

High radix montgomery multipliers for residue arithmetic channels on FPGAs

Yinan Kong^*

^*Corresponding author for this work

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

1 Citation (Scopus)

Abstract

This work targets an efficient Montgomery Modular Multiplier for use in the channels of a Residue Number System (RNS). It is implemented on FPGA and optimized by attempting and evaluating the high radix techniques of the Montgomery Algorithm. The usual correction shift step at the end is proved to be infeasible. The resulting multiplier achieves 15ns for a modular multiplication using high radix without correction shift.

Original language	English
Title of host publication	Future Intelligent Information Systems
Editors	Dehuai Zeng
Place of Publication	Berlin; Heidelberg
Publisher	Springer, Springer Nature
Pages	23-30
Number of pages	8
Volume	86
ISBN (Electronic)	9783642197062
ISBN (Print)	9783642197055
DOIs	https://doi.org/10.1007/978-3-642-19706-2_4
Publication status	Published - 2011
Event	2010 International Conference on Electrical and Electronics Engineering, ICEEE 2010 - Wuhan, China Duration: 4 Dec 2010 → 5 Dec 2010

Publication series

Name	Lecture Notes in Electrical Engineering
Number	VOL. 1
Volume	86 LNEE
ISSN (Print)	18761100
ISSN (Electronic)	18761119

Other

Other	2010 International Conference on Electrical and Electronics Engineering, ICEEE 2010
Country/Territory	China
City	Wuhan
Period	4/12/10 → 5/12/10

Keywords

Digital Arithmetic
FPGA
Montgomery Modular Multiplication
Public-Key Cryptosystems
the Residue Number System

Access to Document

10.1007/978-3-642-19706-2_4

Cite this

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title = "High radix montgomery multipliers for residue arithmetic channels on FPGAs",

abstract = "This work targets an efficient Montgomery Modular Multiplier for use in the channels of a Residue Number System (RNS). It is implemented on FPGA and optimized by attempting and evaluating the high radix techniques of the Montgomery Algorithm. The usual correction shift step at the end is proved to be infeasible. The resulting multiplier achieves 15ns for a modular multiplication using high radix without correction shift.",

keywords = "Digital Arithmetic, FPGA, Montgomery Modular Multiplication, Public-Key Cryptosystems, the Residue Number System",

author = "Yinan Kong",

year = "2011",

doi = "10.1007/978-3-642-19706-2_4",

language = "English",

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volume = "86",

series = "Lecture Notes in Electrical Engineering",

publisher = "Springer, Springer Nature",

number = "VOL. 1",

pages = "23--30",

editor = "Dehuai Zeng",

booktitle = "Future Intelligent Information Systems",

address = "United States",

note = "2010 International Conference on Electrical and Electronics Engineering, ICEEE 2010 ; Conference date: 04-12-2010 Through 05-12-2010",

}

Kong, Y 2011, High radix montgomery multipliers for residue arithmetic channels on FPGAs. in D Zeng (ed.), Future Intelligent Information Systems. vol. 86, Lecture Notes in Electrical Engineering, no. VOL. 1, vol. 86 LNEE, Springer, Springer Nature, Berlin; Heidelberg, pp. 23-30, 2010 International Conference on Electrical and Electronics Engineering, ICEEE 2010, Wuhan, China, 4/12/10. https://doi.org/10.1007/978-3-642-19706-2_4

High radix montgomery multipliers for residue arithmetic channels on FPGAs. / Kong, Yinan.
Future Intelligent Information Systems. ed. / Dehuai Zeng. Vol. 86 Berlin; Heidelberg: Springer, Springer Nature, 2011. p. 23-30 (Lecture Notes in Electrical Engineering; Vol. 86 LNEE, No. VOL. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AB - This work targets an efficient Montgomery Modular Multiplier for use in the channels of a Residue Number System (RNS). It is implemented on FPGA and optimized by attempting and evaluating the high radix techniques of the Montgomery Algorithm. The usual correction shift step at the end is proved to be infeasible. The resulting multiplier achieves 15ns for a modular multiplication using high radix without correction shift.

KW - Digital Arithmetic

KW - FPGA

KW - Montgomery Modular Multiplication

KW - Public-Key Cryptosystems

KW - the Residue Number System

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High radix montgomery multipliers for residue arithmetic channels on FPGAs

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