High speed array computer for dynamic time warping

D. J. Burr*, Bryan Ackland, Neil Weste

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

A CMOS integrated array processor for computing the dynamic time warp algorithm is described. It allows many popular variations including LPC and frequency domain representations of speech. High speed is obtained by extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic application using 40 nine-component LPC vectors per word permits 10,000 word comparisons per second or, equivalently, real time recognition of a 10,000 word vocabulary.

Original languageEnglish
Pages (from-to)471-474
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume2
Publication statusPublished - 1981

Fingerprint Dive into the research topics of 'High speed array computer for dynamic time warping'. Together they form a unique fingerprint.

  • Cite this