ICEPOLE: high-speed, hardware-oriented authenticated encryption

Paweł Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik

Research output: Contribution to journalConference paperpeer-review

12 Citations (Scopus)

Abstract

This paper introduces our dedicated authenticated encryption scheme ICEPOLE. ICEPOLE is a high-speed hardware-oriented scheme, suitable for high-throughput network nodes or generally any environment where specialized hardware (such as FPGAs or ASICs) can be used to provide high data processing rates. ICEPOLE-128 (the primary ICEPOLE variant) is very fast. On the modern FPGA device Virtex 6, a basic iterative architecture of ICEPOLE reaches 41 Gbits/s, which is over 10 times faster than the equivalent implementation of AES-128-GCM. The throughput-to-area ratio is also substantially better when compared to AES-128-GCM. We have carefully examined the security of the algorithm through a range of cryptanalytic techniques and our findings indicate that ICEPOLE offers high security level.

Original languageEnglish
Pages (from-to)392-413
Number of pages22
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume8731
DOIs
Publication statusPublished - 2014
EventInternational workshop on cryptographic hardware and embedded systems (16th : 2014) - Busan, Korea, Democratic People's Republic of
Duration: 23 Sep 201426 Sep 2014

Keywords

  • Authenticated cipher
  • Authenticated encryption scheme
  • ICEPOLE

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