An investigation into the feasibility of implementing private key data encryption algorithms in gate array form is reported. It is found that current generation devices do not yet possess sufficient fabrication density to implement the Data Encryption Standard, however they can easily cater for RC5. Inherent concurrency in the underlying algorithms (eg. repeated rounds) is exploited wherever possible by way of hardware pipelining. This results in superior performance compared with software implementations (assuming similar clock rates), enabling us to generate one cryptogram per clock cycle. The study concludes by making a couple of pertinent comments regarding future capabilities of gate arrays from the perspective of data encryption.
|Number of pages||11|
|Journal||Journal of Electrical and Electronics Engineering, Australia|
|Publication status||Published - Dec 1999|