Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets

Ediz Cetin, Oliver Diessel, Lingkan Gong

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

3 Citations (Scopus)

Abstract

Field-Programmable Gate Arrays (FPGAS) provide an ideal platform for meeting the performance, cost and flexibility requirements of on-board processing in spacebourne applications. However, given the reliance on SRAM-based configuration memory, off-the-shelf FPGAS are vulnerable to radiation-induced Single Event Upsets (SEUs). The detection and mitigation of the effects of SEUs is therefore of paramount importance. Moreover, in time critical applications, it is also desirable to detect and recover from errors rapidly. Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we address the speed penalty incurred with such techniques and provide a generalized approach for alleviating it. The results indicate that the speed penalty can be greatly reduced enabling rapid recovery from SEUs in reconfigurable hardware.

Original languageEnglish
Title of host publicationISCAS 2015
Subtitle of host publicationProceedings of the 2015 IEEE International Symposium on Circuits and Systems
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1190-1193
Number of pages4
ISBN (Electronic)9781479983919
DOIs
Publication statusPublished - 27 Jul 2015
Externally publishedYes
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period24/05/1527/05/15

Keywords

  • fault tolerance
  • radiation induced errors
  • reconfigurable hardware

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