Pattern matching by dynamic time warp has recently been widely applied in the fields of speech and visual pattern recognition. A new approach to this technique that is based on an orthogonal array of simple processing elements is presented. The approach emphasizes using parallel computation and pipelined data flow to achieve extremely high throughput. The internal architecture of the basic processing element and an integrated CMOS implementation are described. Simulation estimates indicate performance gains of up to 200:1 over existing techniques.
|Number of pages||19|
|Journal||Conference Proceedings - Annual Symposium on Computer Architecture|
|Publication status||Published - 1981|