Investigation on the topological configuration of magnetic current limiter for the protection of power semiconductor devices

S. C. Mukhopadhyay*, F. P. Dawson, M. Iwahara, S. Yamada

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper describes different topological configurations for a passive magnetic current limiter consisting of a permanent magnet and saturable core. The fabricated model for a series/parallel biasing mode, and single/three phase supply system is described. The transient simulation has been carried out with the help of the tableau approach and experiments have been performed to validate the simulation results. The feasibility of applying the current limiter for the protection of power semiconductor devices in moderately low voltage applications is investigated.

Original languageEnglish
Pages (from-to)2463-2470
Number of pages8
JournalConference Record - IAS Annual Meeting (IEEE Industry Applications Society)
Volume4
Publication statusPublished - 2000
Externally publishedYes

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