Low-cost integrated circuit tester

D. J. Skellern*, M. E. Johnson, P. C B Henderson

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review


Hardware and software of a low-cost computer aided test system, designed for user testing of custom integrated circuits, are described. The system uses a memory-driven latch device to provide functional testing of chips with up to 40 pins at speeds up to 15 MHz. Several approaches to providing a hardware test capability are discussed.

Original languageEnglish
Title of host publicationIREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia)
Place of PublicationSydney, NSW
PublisherInst of Radio & Electronics Engineers Australia
Number of pages3
Publication statusPublished - 1983
Externally publishedYes


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