Abstract
Hardware and software of a low-cost computer aided test system, designed for user testing of custom integrated circuits, are described. The system uses a memory-driven latch device to provide functional testing of chips with up to 40 pins at speeds up to 15 MHz. Several approaches to providing a hardware test capability are discussed.
Original language | English |
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Title of host publication | IREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia) |
Place of Publication | Sydney, NSW |
Publisher | Inst of Radio & Electronics Engineers Australia |
Pages | 24-26 |
Number of pages | 3 |
Publication status | Published - 1983 |
Externally published | Yes |