Low-cost integrated circuit tester

D. J. Skellern; M. E. Johnson; P. C B Henderson

Low-cost integrated circuit tester

D. J. Skellern^*, M. E. Johnson, P. C B Henderson

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

Hardware and software of a low-cost computer aided test system, designed for user testing of custom integrated circuits, are described. The system uses a memory-driven latch device to provide functional testing of chips with up to 40 pins at speeds up to 15 MHz. Several approaches to providing a hardware test capability are discussed.

Original language	English
Title of host publication	IREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia)
Place of Publication	Sydney, NSW
Publisher	Inst of Radio & Electronics Engineers Australia
Pages	24-26
Number of pages	3
Publication status	Published - 1983
Externally published	Yes

Cite this

@inproceedings{abb86b178a61420ebab371c95cc10401,

title = "Low-cost integrated circuit tester",

abstract = "Hardware and software of a low-cost computer aided test system, designed for user testing of custom integrated circuits, are described. The system uses a memory-driven latch device to provide functional testing of chips with up to 40 pins at speeds up to 15 MHz. Several approaches to providing a hardware test capability are discussed.",

author = "Skellern, \{D. J.\} and Johnson, \{M. E.\} and Henderson, \{P. C B\}",

year = "1983",

language = "English",

pages = "24--26",

booktitle = "IREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia)",

publisher = "Inst of Radio \& Electronics Engineers Australia",

}

Low-cost integrated circuit tester. / Skellern, D. J.; Johnson, M. E.; Henderson, P. C B.
IREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia). Sydney, NSW: Inst of Radio & Electronics Engineers Australia, 1983. p. 24-26.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

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AU - Johnson, M. E.

AU - Henderson, P. C B

PY - 1983

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AB - Hardware and software of a low-cost computer aided test system, designed for user testing of custom integrated circuits, are described. The system uses a memory-driven latch device to provide functional testing of chips with up to 40 pins at speeds up to 15 MHz. Several approaches to providing a hardware test capability are discussed.

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M3 - Conference proceeding contribution

AN - SCOPUS:0020864956

SP - 24

EP - 26

BT - IREECON International (Convention Digest) (Institution of Radio and Electronics Engineers Australia)

PB - Inst of Radio & Electronics Engineers Australia

CY - Sydney, NSW

ER -

Low-cost integrated circuit tester

Abstract

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