Low power 50 MHz FFT processor with cyclic extension and shaping filter

M. Bickerstaff; T. Arivoli; P. J. Ryan; N. Weste; D. Skellern

doi:10.1109/ASPDAC.1998.669493

Low power 50 MHz FFT processor with cyclic extension and shaping filter

M. Bickerstaff^*, T. Arivoli, P. J. Ryan, N. Weste, D. Skellern

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

2 Citations (Scopus)

Abstract

The architecture and design of a low power 50 MHz fast Fourier transform (FFT) chip for a 50 Mbs wireless local area network (WLAN) modem are presented. The chip was fabricated and was fully functional at rated speed at 2.5 volts. The 110,000-transistor chip is implemented in 0.6 μm complementary metal oxide semiconductor (CMOS), operates worst case at 50 MHz. The chip served to validate and calibrate a new design methodology which enables the rapid capture of high performance digital blocks and the automated design of small, low power layouts.

Original language	English
Title of host publication	Proceedings of the ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	335-336
Number of pages	2
ISBN (Print)	0780344251
DOIs	https://doi.org/10.1109/ASPDAC.1998.669493
Publication status	Published - 1998
Event	3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98 - Yokohama, Japan Duration: 10 Feb 1998 → 13 Feb 1998

Conference

Conference	3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98
Country/Territory	Japan
City	Yokohama
Period	10/02/98 → 13/02/98

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10.1109/ASPDAC.1998.669493

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title = "Low power 50 MHz FFT processor with cyclic extension and shaping filter",

abstract = "The architecture and design of a low power 50 MHz fast Fourier transform (FFT) chip for a 50 Mbs wireless local area network (WLAN) modem are presented. The chip was fabricated and was fully functional at rated speed at 2.5 volts. The 110,000-transistor chip is implemented in 0.6 μm complementary metal oxide semiconductor (CMOS), operates worst case at 50 MHz. The chip served to validate and calibrate a new design methodology which enables the rapid capture of high performance digital blocks and the automated design of small, low power layouts.",

author = "M. Bickerstaff and T. Arivoli and Ryan, {P. J.} and N. Weste and D. Skellern",

year = "1998",

doi = "10.1109/ASPDAC.1998.669493",

language = "English",

isbn = "0780344251",

pages = "335--336",

booktitle = "Proceedings of the ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98 ; Conference date: 10-02-1998 Through 13-02-1998",

}

Bickerstaff, M, Arivoli, T, Ryan, PJ, Weste, N & Skellern, D 1998, Low power 50 MHz FFT processor with cyclic extension and shaping filter. in Proceedings of the ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 335-336, 3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98, Yokohama, Japan, 10/02/98. https://doi.org/10.1109/ASPDAC.1998.669493

Low power 50 MHz FFT processor with cyclic extension and shaping filter. / Bickerstaff, M.; Arivoli, T.; Ryan, P. J.; Weste, N.; Skellern, D.

Proceedings of the ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 1998. p. 335-336.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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T1 - Low power 50 MHz FFT processor with cyclic extension and shaping filter

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AU - Arivoli, T.

AU - Ryan, P. J.

AU - Weste, N.

AU - Skellern, D.

PY - 1998

Y1 - 1998

N2 - The architecture and design of a low power 50 MHz fast Fourier transform (FFT) chip for a 50 Mbs wireless local area network (WLAN) modem are presented. The chip was fabricated and was fully functional at rated speed at 2.5 volts. The 110,000-transistor chip is implemented in 0.6 μm complementary metal oxide semiconductor (CMOS), operates worst case at 50 MHz. The chip served to validate and calibrate a new design methodology which enables the rapid capture of high performance digital blocks and the automated design of small, low power layouts.

AB - The architecture and design of a low power 50 MHz fast Fourier transform (FFT) chip for a 50 Mbs wireless local area network (WLAN) modem are presented. The chip was fabricated and was fully functional at rated speed at 2.5 volts. The 110,000-transistor chip is implemented in 0.6 μm complementary metal oxide semiconductor (CMOS), operates worst case at 50 MHz. The chip served to validate and calibrate a new design methodology which enables the rapid capture of high performance digital blocks and the automated design of small, low power layouts.

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DO - 10.1109/ASPDAC.1998.669493

M3 - Conference proceeding contribution

AN - SCOPUS:0032218655

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BT - Proceedings of the ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998

PB - Institute of Electrical and Electronics Engineers (IEEE)

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T2 - 3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98

Y2 - 10 February 1998 through 13 February 1998

ER -

Low power 50 MHz FFT processor with cyclic extension and shaping filter

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