Low power 50 MHz FFT processor with cyclic extension and shaping filter

M. Bickerstaff*, T. Arivoli, P. J. Ryan, N. Weste, D. Skellern

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

    2 Citations (Scopus)

    Abstract

    The architecture and design of a low power 50 MHz fast Fourier transform (FFT) chip for a 50 Mbs wireless local area network (WLAN) modem are presented. The chip was fabricated and was fully functional at rated speed at 2.5 volts. The 110,000-transistor chip is implemented in 0.6 μm complementary metal oxide semiconductor (CMOS), operates worst case at 50 MHz. The chip served to validate and calibrate a new design methodology which enables the rapid capture of high performance digital blocks and the automated design of small, low power layouts.

    Original languageEnglish
    Title of host publication Proceedings of the ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998
    Place of PublicationPiscataway, NJ
    PublisherInstitute of Electrical and Electronics Engineers (IEEE)
    Pages335-336
    Number of pages2
    ISBN (Print)0780344251
    DOIs
    Publication statusPublished - 1998
    Event3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98 - Yokohama, Japan
    Duration: 10 Feb 199813 Feb 1998

    Conference

    Conference3rd Meeting of the Asia and South-Pacific Design Automation Conference (ASP-DAC 98) / EDA Techno Fair 98
    CountryJapan
    CityYokohama
    Period10/02/9813/02/98

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