Low power 50MHz FFT processor with cyclic extension and shaping filter

N. Weste; M. Bickerstaff; T. Arivoli; P. J. Ryan; D. J. Skellern; T. M. Percival

Low power 50MHz FFT processor with cyclic extension and shaping filter

N. Weste^*, M. Bickerstaff, T. Arivoli, P. J. Ryan, D. J. Skellern, T. M. Percival

^*Corresponding author for this work

Faculty of Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

This paper presents the architecture, design and implementation of a 16-point FFT processor for a high-speed Wireless Local Area Network. The 110,000-transistor chip is implemented in 0.6μm TLM CMOS, operates worst-case at 50MHz and a supply voltage of 2.5 volts, and consumes 80 mW. It represents one of the significant computational blocks in a discrete multitone modem currently being designed at Macquarie University.

Original language	English
Title of host publication	Proceedings of the Australian Microelectronics Conference
Subtitle of host publication	microelectronics, technology today for the future.
Place of Publication	Milsons Point, NSW
Publisher	IREE Society
Pages	36-40
Number of pages	5
ISBN (Print)	0909394431
Publication status	Published - 1997
Event	Proceedings of the 1997 14th Australian Microelectronics Conference, MICRO - Melbourne, Australia Duration: 29 Sept 1997 → 1 Oct 1997

Other

Other	Proceedings of the 1997 14th Australian Microelectronics Conference, MICRO
City	Melbourne, Australia
Period	29/09/97 → 1/10/97

Keywords

Program processors
Local area networks
Electric filters
Microprocessor chips
CMOS integrated circuits
Modems
Digital signal processing
Analog to digital conversion
Digital to analog conversion

Cite this

@inproceedings{3a591ce5632a4aa89afbee498082d542,

title = "Low power 50MHz FFT processor with cyclic extension and shaping filter",

abstract = "This paper presents the architecture, design and implementation of a 16-point FFT processor for a high-speed Wireless Local Area Network. The 110,000-transistor chip is implemented in 0.6μm TLM CMOS, operates worst-case at 50MHz and a supply voltage of 2.5 volts, and consumes 80 mW. It represents one of the significant computational blocks in a discrete multitone modem currently being designed at Macquarie University.",

keywords = "Program processors, Local area networks, Electric filters, Microprocessor chips, CMOS integrated circuits, Modems, Digital signal processing, Analog to digital conversion, Digital to analog conversion",

author = "N. Weste and M. Bickerstaff and T. Arivoli and Ryan, {P. J.} and Skellern, {D. J.} and Percival, {T. M.}",

year = "1997",

language = "English",

isbn = "0909394431",

pages = "36--40",

booktitle = "Proceedings of the Australian Microelectronics Conference",

publisher = "IREE Society",

note = "Proceedings of the 1997 14th Australian Microelectronics Conference, MICRO ; Conference date: 29-09-1997 Through 01-10-1997",

}

Weste, N, Bickerstaff, M, Arivoli, T, Ryan, PJ, Skellern, DJ & Percival, TM 1997, Low power 50MHz FFT processor with cyclic extension and shaping filter. in Proceedings of the Australian Microelectronics Conference: microelectronics, technology today for the future.. IREE Society, Milsons Point, NSW, pp. 36-40, Proceedings of the 1997 14th Australian Microelectronics Conference, MICRO, Melbourne, Australia, 29/09/97.

Low power 50MHz FFT processor with cyclic extension and shaping filter. / Weste, N.; Bickerstaff, M.; Arivoli, T. et al.
Proceedings of the Australian Microelectronics Conference: microelectronics, technology today for the future.. Milsons Point, NSW: IREE Society, 1997. p. 36-40.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Low power 50MHz FFT processor with cyclic extension and shaping filter

AU - Weste, N.

AU - Bickerstaff, M.

AU - Arivoli, T.

AU - Ryan, P. J.

AU - Skellern, D. J.

AU - Percival, T. M.

PY - 1997

Y1 - 1997

N2 - This paper presents the architecture, design and implementation of a 16-point FFT processor for a high-speed Wireless Local Area Network. The 110,000-transistor chip is implemented in 0.6μm TLM CMOS, operates worst-case at 50MHz and a supply voltage of 2.5 volts, and consumes 80 mW. It represents one of the significant computational blocks in a discrete multitone modem currently being designed at Macquarie University.

AB - This paper presents the architecture, design and implementation of a 16-point FFT processor for a high-speed Wireless Local Area Network. The 110,000-transistor chip is implemented in 0.6μm TLM CMOS, operates worst-case at 50MHz and a supply voltage of 2.5 volts, and consumes 80 mW. It represents one of the significant computational blocks in a discrete multitone modem currently being designed at Macquarie University.

KW - Program processors

KW - Local area networks

KW - Electric filters

KW - Microprocessor chips

KW - CMOS integrated circuits

KW - Modems

KW - Digital signal processing

KW - Analog to digital conversion

KW - Digital to analog conversion

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M3 - Conference proceeding contribution

AN - SCOPUS:0031385205

SN - 0909394431

SP - 36

EP - 40

BT - Proceedings of the Australian Microelectronics Conference

PB - IREE Society

CY - Milsons Point, NSW

T2 - Proceedings of the 1997 14th Australian Microelectronics Conference, MICRO

Y2 - 29 September 1997 through 1 October 1997

ER -

Low power 50MHz FFT processor with cyclic extension and shaping filter

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