Low power 50MHz FFT processor with cyclic extension and shaping filter

N. Weste*, M. Bickerstaff, T. Arivoli, P. J. Ryan, D. J. Skellern, T. M. Percival

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

Abstract

This paper presents the architecture, design and implementation of a 16-point FFT processor for a high-speed Wireless Local Area Network. The 110,000-transistor chip is implemented in 0.6μm TLM CMOS, operates worst-case at 50MHz and a supply voltage of 2.5 volts, and consumes 80 mW. It represents one of the significant computational blocks in a discrete multitone modem currently being designed at Macquarie University.

Original languageEnglish
Title of host publicationProceedings of the Australian Microelectronics Conference
Subtitle of host publicationmicroelectronics, technology today for the future.
Place of PublicationMilsons Point, NSW
PublisherIREE Society
Pages36-40
Number of pages5
ISBN (Print)0909394431
Publication statusPublished - 1997
EventProceedings of the 1997 14th Australian Microelectronics Conference, MICRO - Melbourne, Australia
Duration: 29 Sep 19971 Oct 1997

Other

OtherProceedings of the 1997 14th Australian Microelectronics Conference, MICRO
CityMelbourne, Australia
Period29/09/971/10/97

Keywords

  • Program processors
  • Local area networks
  • Electric filters
  • Microprocessor chips
  • CMOS integrated circuits
  • Modems
  • Digital signal processing
  • Analog to digital conversion
  • Digital to analog conversion

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