Managing verification activities using SVM

Bill Aldrich; Ansgar Fehnker; Peter H. Feiler; Zhi Han; Bruce H. Krogh; Eric Lim; Shiva Sivashankar

doi:10.1007/978-3-540-30482-1_13

Managing verification activities using SVM

Bill Aldrich, Ansgar Fehnker, Peter H. Feiler, Zhi Han, Bruce H. Krogh, Eric Lim, Shiva Sivashankar

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

2 Citations (Scopus)

Abstract

SVM (System Verification Manager) manages the application of verification methods for model-based development of embedded systems by providing integrated representations of requirements, system architecture, models and verification methods. Developed in Java within MATLAB®, SVM supports all types of tools for modelling and verification through an extensible framework of data and coding structures. This paper presents the main features of SVM and illustrates its application to embedded control and signal processing systems.

Original language	English
Title of host publication	Formal Methods and Software Engineering
Subtitle of host publication	6th International Conference on Formal Engineering Methods, ICFEM 2004 Seattle, WA, USA, November 8-12, 2004, Proceedings
Editors	Jim Davies, Wolfram Schulte, Michael Barnett
Place of Publication	Berlin
Publisher	Springer, Springer Nature
Pages	61-75
Number of pages	15
ISBN (Print)	9783540238416, 3540238417
DOIs	https://doi.org/10.1007/978-3-540-30482-1_13
Publication status	Published - 2004
Externally published	Yes
Event	6th International Conference on Formal Engineering Methods, ICFEM 2004 - Seattle, United States Duration: 8 Nov 2004 → 12 Nov 2004

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer
Volume	3308
ISSN (Print)	0302-9743

Conference

Conference	6th International Conference on Formal Engineering Methods, ICFEM 2004
Country/Territory	United States
City	Seattle
Period	8/11/04 → 12/11/04

Access to Document

10.1007/978-3-540-30482-1_13

Cite this

Aldrich, B., Fehnker, A., Feiler, P. H., Han, Z., Krogh, B. H., Lim, E., & Sivashankar, S. (2004). Managing verification activities using SVM. In J. Davies, W. Schulte, & M. Barnett (Eds.), Formal Methods and Software Engineering: 6th International Conference on Formal Engineering Methods, ICFEM 2004 Seattle, WA, USA, November 8-12, 2004, Proceedings (pp. 61-75). (Lecture Notes in Computer Science; Vol. 3308). Springer, Springer Nature. https://doi.org/10.1007/978-3-540-30482-1_13

Aldrich, Bill ; Fehnker, Ansgar ; Feiler, Peter H. et al. / Managing verification activities using SVM. Formal Methods and Software Engineering: 6th International Conference on Formal Engineering Methods, ICFEM 2004 Seattle, WA, USA, November 8-12, 2004, Proceedings. editor / Jim Davies ; Wolfram Schulte ; Michael Barnett. Berlin : Springer, Springer Nature, 2004. pp. 61-75 (Lecture Notes in Computer Science).

@inproceedings{28ba26c244d24768af427546b552158d,

title = "Managing verification activities using SVM",

abstract = "SVM (System Verification Manager) manages the application of verification methods for model-based development of embedded systems by providing integrated representations of requirements, system architecture, models and verification methods. Developed in Java within MATLAB{\textregistered}, SVM supports all types of tools for modelling and verification through an extensible framework of data and coding structures. This paper presents the main features of SVM and illustrates its application to embedded control and signal processing systems.",

author = "Bill Aldrich and Ansgar Fehnker and Feiler, {Peter H.} and Zhi Han and Krogh, {Bruce H.} and Eric Lim and Shiva Sivashankar",

year = "2004",

doi = "10.1007/978-3-540-30482-1_13",

language = "English",

isbn = "9783540238416",

series = "Lecture Notes in Computer Science",

publisher = "Springer, Springer Nature",

pages = "61--75",

editor = "Jim Davies and Wolfram Schulte and Michael Barnett",

booktitle = "Formal Methods and Software Engineering",

address = "United States",

note = "6th International Conference on Formal Engineering Methods, ICFEM 2004 ; Conference date: 08-11-2004 Through 12-11-2004",

}

Aldrich, B, Fehnker, A, Feiler, PH, Han, Z, Krogh, BH, Lim, E & Sivashankar, S 2004, Managing verification activities using SVM. in J Davies, W Schulte & M Barnett (eds), Formal Methods and Software Engineering: 6th International Conference on Formal Engineering Methods, ICFEM 2004 Seattle, WA, USA, November 8-12, 2004, Proceedings. Lecture Notes in Computer Science, vol. 3308, Springer, Springer Nature, Berlin, pp. 61-75, 6th International Conference on Formal Engineering Methods, ICFEM 2004, Seattle, Washington, United States, 8/11/04. https://doi.org/10.1007/978-3-540-30482-1_13

Managing verification activities using SVM. / Aldrich, Bill; Fehnker, Ansgar; Feiler, Peter H. et al.
Formal Methods and Software Engineering: 6th International Conference on Formal Engineering Methods, ICFEM 2004 Seattle, WA, USA, November 8-12, 2004, Proceedings. ed. / Jim Davies; Wolfram Schulte; Michael Barnett. Berlin: Springer, Springer Nature, 2004. p. 61-75 (Lecture Notes in Computer Science; Vol. 3308).

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Managing verification activities using SVM

AU - Aldrich, Bill

AU - Fehnker, Ansgar

AU - Feiler, Peter H.

AU - Han, Zhi

AU - Krogh, Bruce H.

AU - Lim, Eric

AU - Sivashankar, Shiva

PY - 2004

Y1 - 2004

N2 - SVM (System Verification Manager) manages the application of verification methods for model-based development of embedded systems by providing integrated representations of requirements, system architecture, models and verification methods. Developed in Java within MATLAB®, SVM supports all types of tools for modelling and verification through an extensible framework of data and coding structures. This paper presents the main features of SVM and illustrates its application to embedded control and signal processing systems.

AB - SVM (System Verification Manager) manages the application of verification methods for model-based development of embedded systems by providing integrated representations of requirements, system architecture, models and verification methods. Developed in Java within MATLAB®, SVM supports all types of tools for modelling and verification through an extensible framework of data and coding structures. This paper presents the main features of SVM and illustrates its application to embedded control and signal processing systems.

U2 - 10.1007/978-3-540-30482-1_13

DO - 10.1007/978-3-540-30482-1_13

M3 - Conference proceeding contribution

SN - 9783540238416

SN - 3540238417

T3 - Lecture Notes in Computer Science

SP - 61

EP - 75

BT - Formal Methods and Software Engineering

A2 - Davies, Jim

A2 - Schulte, Wolfram

A2 - Barnett, Michael

PB - Springer, Springer Nature

CY - Berlin

T2 - 6th International Conference on Formal Engineering Methods, ICFEM 2004

Y2 - 8 November 2004 through 12 November 2004

ER -

Aldrich B, Fehnker A, Feiler PH, Han Z, Krogh BH, Lim E et al. Managing verification activities using SVM. In Davies J, Schulte W, Barnett M, editors, Formal Methods and Software Engineering: 6th International Conference on Formal Engineering Methods, ICFEM 2004 Seattle, WA, USA, November 8-12, 2004, Proceedings. Berlin: Springer, Springer Nature. 2004. p. 61-75. (Lecture Notes in Computer Science). doi: 10.1007/978-3-540-30482-1_13

Managing verification activities using SVM

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this