Pulse characteristics exhibit a seemingly chaotic relation to timing and bias, which is evidence of memory. Charge trapping within field-effect transistors is acknowledged as a significant source of memory. However, the challenge for interpretation of pulse and large-signal RF measurements is the large number of permutations of trap polarity, trap location, sources of trapped charge, and number of trap sites. This session will attempt to demystify the understanding of trapping processes and demonstrate that a simple generic model of a trap center, suitable for implementation in circuit simulators, can become the focus for interpreting transistor memory. Along with a good thermal-electric model, it is possible to classify various pulse characteristics, so that the nature of traps can be inferred. The interplay with both heating and channel breakdown and the relationship to linearity are interesting aspects that will be considered.
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||40|
|Place of Publication||New York|
|Publication status||Published - 2009|