Modeling of back-gate effects on gate-induced drain leakage and gate currents in UTB SOI MOSFETs

Yen Kai Lin, Pragya Kushwaha, Harshit Agarwal, Huan Lin Chang, Juan Pablo Duarte, Angada B. Sachid, Sourabh Khandelwal, Sayeef Salahuddin, Chenming Hu

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

Original languageEnglish
Pages (from-to)3986 - 3990
Number of pages5
JournalIEEE Transactions on Electron Devices
Issue number10
Publication statusPublished - 2017


  • Back gate
  • Berkeley short-channel IGFET model-independent multi-gate (BSIM-IMG)
  • Data models
  • gate leakage
  • GIDL
  • Leakage currents
  • Logic gates
  • modeling
  • MOSFET circuits
  • Semiconductor device modeling
  • Tunneling


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