We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.
|Number of pages||6|
|Journal||IEEE Transactions on Electron Devices|
|Publication status||Published - 1 May 2016|
- short channel
- zero-V MOSFET