Modeling of Subsurface Leakage Current in Low V-TH Short Channel MOSFET at Accumulation Bias

Yen Kai Lin; Sourabh Khandelwal; Aditya Sankar Medury; Harshit Agarwal; Huan Lin Chang; Yogesh Singh Chauhan; Chenming Hu

doi:10.1109/TED.2016.2544818

Modeling of Subsurface Leakage Current in Low V-TH Short Channel MOSFET at Accumulation Bias

Yen Kai Lin, Sourabh Khandelwal, Aditya Sankar Medury, Harshit Agarwal, Huan Lin Chang, Yogesh Singh Chauhan, Chenming Hu

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (V_DS), gate-to-source voltage ( V_GS), gate length ( L_G), substrate doping concentration ( N_sub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.

Original language	English
Article number	7448409
Pages (from-to)	1840-1845
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	63
Issue number	5
DOIs	https://doi.org/10.1109/TED.2016.2544818
Publication status	Published - 1 May 2016
Externally published	Yes

Keywords

BSIM6
leakage
modeling
short channel
subsurface
zero-V MOSFET

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10.1109/TED.2016.2544818

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abstract = "We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( \$T\$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.",

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T1 - Modeling of Subsurface Leakage Current in Low V-TH Short Channel MOSFET at Accumulation Bias

AU - Lin, Yen Kai

AU - Khandelwal, Sourabh

AU - Medury, Aditya Sankar

AU - Agarwal, Harshit

AU - Chang, Huan Lin

AU - Chauhan, Yogesh Singh

AU - Hu, Chenming

PY - 2016/5/1

Y1 - 2016/5/1

N2 - We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.

AB - We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage ( VGS), gate length ( LG), substrate doping concentration ( Nsub), and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.

KW - BSIM6

KW - leakage

KW - modeling

KW - short channel

KW - subsurface

KW - zero-V MOSFET

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DO - 10.1109/TED.2016.2544818

M3 - Article

AN - SCOPUS:84979493344

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SP - 1840

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 5

M1 - 7448409

ER -

Modeling of Subsurface Leakage Current in Low V-TH Short Channel MOSFET at Accumulation Bias

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Keywords

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