Modeling SiGe FinFETs with Thin Fin and Current-Dependent Source/Drain Resistance

Sourabh Khandelwal, Juan Pablo Duarte, Aditya Medury, Yogesh S. Chauhan, Sayeef Salahuddin, Chenming Hu

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W-{\textrm {fin}} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data.

Original languageEnglish
Article number7112615
Pages (from-to)636-638
Number of pages3
JournalIEEE Electron Device Letters
Volume36
Issue number7
DOIs
Publication statusPublished - 1 Jul 2015
Externally publishedYes

Keywords

  • BSIM-CMG
  • Compact Model
  • FinFETs
  • Silicon Germanium (SiGe)

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