Modeling SiGe FinFETs with Thin Fin and Current-Dependent Source/Drain Resistance

Sourabh Khandelwal; Juan Pablo Duarte; Aditya Medury; Yogesh S. Chauhan; Sayeef Salahuddin; Chenming Hu

doi:10.1109/LED.2015.2437794

Modeling SiGe FinFETs with Thin Fin and Current-Dependent Source/Drain Resistance

Sourabh Khandelwal, Juan Pablo Duarte, Aditya Medury, Yogesh S. Chauhan, Sayeef Salahuddin, Chenming Hu

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W-{\textrm {fin}} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data.

Original language	English
Article number	7112615
Pages (from-to)	636-638
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	36
Issue number	7
DOIs	https://doi.org/10.1109/LED.2015.2437794
Publication status	Published - 1 Jul 2015
Externally published	Yes

Keywords

BSIM-CMG
Compact Model
FinFETs
Silicon Germanium (SiGe)

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10.1109/LED.2015.2437794

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title = "Modeling SiGe FinFETs with Thin Fin and Current-Dependent Source/Drain Resistance",

abstract = "In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W-{\textrm {fin}} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data.",

keywords = "BSIM-CMG, Compact Model, FinFETs, Silicon Germanium (SiGe)",

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AU - Khandelwal, Sourabh

AU - Duarte, Juan Pablo

AU - Medury, Aditya

AU - Chauhan, Yogesh S.

AU - Salahuddin, Sayeef

AU - Hu, Chenming

PY - 2015/7/1

Y1 - 2015/7/1

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AB - In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W-{\textrm {fin}} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data.

KW - BSIM-CMG

KW - Compact Model

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KW - Silicon Germanium (SiGe)

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Modeling SiGe FinFETs with Thin Fin and Current-Dependent Source/Drain Resistance

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