Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Sourabh Khandelwal; Harshit Agarwal; Juan Pablo Duarte; Kaiman Chan; Sagnik Dey; Yogesh Singh Chauhan; Chenming Hu

doi:10.1109/TCAD.2015.2419626

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current I_edge at the shallow trench isolation edge. Accurate, efficient, and scalable model for I_edge is developed by finding the key differences between I_edge and main device drain current (I_main). It is found that I_edge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to I_main. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

Original language	English
Article number	7079473
Pages (from-to)	1291-1294
Number of pages	4
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	34
Issue number	8
DOIs	https://doi.org/10.1109/TCAD.2015.2419626
Publication status	Published - 1 Aug 2015
Externally published	Yes

Keywords

Analog technology
BSIM6
compact models
parasitic currents
shallow trench isolation (STI) edge effects

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10.1109/TCAD.2015.2419626

Cite this

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title = "Modeling STI Edge Parasitic Current for Accurate Circuit Simulations",

abstract = "We enhance the capability of industry standard compact model BSIM6 to model the parasitic current Iedge at the shallow trench isolation edge. Accurate, efficient, and scalable model for Iedge is developed by finding the key differences between Iedge and main device drain current (Imain). It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.",

keywords = "Analog technology, BSIM6, compact models, parasitic currents, shallow trench isolation (STI) edge effects",

author = "Sourabh Khandelwal and Harshit Agarwal and Duarte, {Juan Pablo} and Kaiman Chan and Sagnik Dey and Chauhan, {Yogesh Singh} and Chenming Hu",

year = "2015",

month = aug,

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doi = "10.1109/TCAD.2015.2419626",

language = "English",

volume = "34",

pages = "1291--1294",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

number = "8",

}

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations. / Khandelwal, Sourabh; Agarwal, Harshit; Duarte, Juan Pablo; Chan, Kaiman; Dey, Sagnik; Chauhan, Yogesh Singh; Hu, Chenming.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 8, 7079473, 01.08.2015, p. 1291-1294.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

AU - Khandelwal, Sourabh

AU - Agarwal, Harshit

AU - Duarte, Juan Pablo

AU - Chan, Kaiman

AU - Dey, Sagnik

AU - Chauhan, Yogesh Singh

AU - Hu, Chenming

PY - 2015/8/1

Y1 - 2015/8/1

N2 - We enhance the capability of industry standard compact model BSIM6 to model the parasitic current Iedge at the shallow trench isolation edge. Accurate, efficient, and scalable model for Iedge is developed by finding the key differences between Iedge and main device drain current (Imain). It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

AB - We enhance the capability of industry standard compact model BSIM6 to model the parasitic current Iedge at the shallow trench isolation edge. Accurate, efficient, and scalable model for Iedge is developed by finding the key differences between Iedge and main device drain current (Imain). It is found that Iedge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to Imain. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

KW - Analog technology

KW - BSIM6

KW - compact models

KW - parasitic currents

KW - shallow trench isolation (STI) edge effects

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DO - 10.1109/TCAD.2015.2419626

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VL - 34

SP - 1291

EP - 1294

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 8

M1 - 7079473

ER -

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

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Keywords

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