Abstract
In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V and I-V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.
Original language | English |
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Pages (from-to) | 6-11 |
Number of pages | 6 |
Journal | Solid-State Electronics |
Volume | 104 |
DOIs | |
Publication status | Published - Feb 2015 |
Externally published | Yes |
Keywords
- BSIM-IMG
- Compact model
- FDSOI
- MOSFET
- Substrate depletion