Modeling the impact of substrate depletion in FDSOI MOSFETs

Pragya Kushwaha*, Navid Paydavosi, Sourabh Khandelwal, Chandan Yadav, Harshit Agarwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

23 Citations (Scopus)

Abstract

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V and I-V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

Original languageEnglish
Pages (from-to)6-11
Number of pages6
JournalSolid-State Electronics
Volume104
DOIs
Publication statusPublished - Feb 2015
Externally publishedYes

Keywords

  • BSIM-IMG
  • Compact model
  • FDSOI
  • MOSFET
  • Substrate depletion

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