Modeling the impact of substrate depletion in FDSOI MOSFETs

Pragya Kushwaha; Navid Paydavosi; Sourabh Khandelwal; Chandan Yadav; Harshit Agarwal; Juan Pablo Duarte; Chenming Hu; Yogesh Singh Chauhan

doi:10.1016/j.sse.2014.11.002

Modeling the impact of substrate depletion in FDSOI MOSFETs

Pragya Kushwaha^*, Navid Paydavosi, Sourabh Khandelwal, Chandan Yadav, Harshit Agarwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

29 Citations (Scopus)

Abstract

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V and I-V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

Original language	English
Pages (from-to)	6-11
Number of pages	6
Journal	Solid-State Electronics
Volume	104
DOIs	https://doi.org/10.1016/j.sse.2014.11.002
Publication status	Published - Feb 2015
Externally published	Yes

Keywords

BSIM-IMG
Compact model
FDSOI
MOSFET
Substrate depletion

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10.1016/j.sse.2014.11.002

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title = "Modeling the impact of substrate depletion in FDSOI MOSFETs",

abstract = "In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V and I-V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.",

keywords = "BSIM-IMG, Compact model, FDSOI, MOSFET, Substrate depletion",

author = "Pragya Kushwaha and Navid Paydavosi and Sourabh Khandelwal and Chandan Yadav and Harshit Agarwal and Duarte, \{Juan Pablo\} and Chenming Hu and Chauhan, \{Yogesh Singh\}",

year = "2015",

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doi = "10.1016/j.sse.2014.11.002",

language = "English",

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journal = "Solid-State Electronics",

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T1 - Modeling the impact of substrate depletion in FDSOI MOSFETs

AU - Kushwaha, Pragya

AU - Paydavosi, Navid

AU - Khandelwal, Sourabh

AU - Yadav, Chandan

AU - Agarwal, Harshit

AU - Duarte, Juan Pablo

AU - Hu, Chenming

AU - Chauhan, Yogesh Singh

PY - 2015/2

Y1 - 2015/2

N2 - In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V and I-V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

AB - In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V and I-V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

KW - BSIM-IMG

KW - Compact model

KW - FDSOI

KW - MOSFET

KW - Substrate depletion

UR - https://www.scopus.com/pages/publications/84912572105

U2 - 10.1016/j.sse.2014.11.002

DO - 10.1016/j.sse.2014.11.002

M3 - Article

AN - SCOPUS:84912572105

SN - 0038-1101

VL - 104

SP - 6

EP - 11

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

Modeling the impact of substrate depletion in FDSOI MOSFETs

Abstract

Keywords

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