Modelling electron trapping effects on gate lag in field effect devices

Saif Uz Zaman, Anthony E. Parker

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

Abstract

Traps at the surface of devices cause delayed response of drain current to a step change of gate voltage. This is known as gate lag. Gate lag is usually caused by surface hole trapping. Traps at the surface are charged negatively during turn-off of the device. The negative charge turns the device further off. After turn-on, these negative charges decay by means of capturing holes, which turns the device further on. However, measurements have shown that electron trapping also occurs during gate pulsing which causes drain current to decrease after turn-on pulse. This paper aims to model this electron trapping effect and combine it with a previously developed hole trapping model.
Original languageEnglish
Title of host publicationProceedings of the WARS2006 Conference
EditorsPhil Wilkinson
Place of PublicationCanberra
PublisherNational Committee Radio Service
Number of pages7
ISBN (Print)0643093184
Publication statusPublished - 2006
EventWorkshop on the Applications of Radio Science (6th : 2006) - Leura, NSW
Duration: 15 Feb 200617 Feb 2006

Workshop

WorkshopWorkshop on the Applications of Radio Science (6th : 2006)
CityLeura, NSW
Period15/02/0617/02/06

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