Optimal ferroelectric parameters for negative capacitance field-effect transistors based on full-chip implementations-part II: scaling of the supply voltage

Sai Pentapati*, Rakesh Perumal, Sourabh Khandelwal, Asif I. Khan, Sung Kyu Lim

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

Negative capacitance field-effect transistors (NCFETs) with optimal ferroelectric parameters provide phenomenal power reduction as discussed in Part I. In this part, we explore the impact of operating voltage on power consumption at the device, gate, and full-chip levels. We first observe that high operating voltages applied to NCFET devices lead to an abrupt increase in both the drain current and the gate capacitance. Furthermore, negative capacitance is lost when the voltage is set too high. On the other hand, the gate capacitance increase still exists, although with smaller magnitude, even at low operating voltages. This helps reduce device delay and eventually full-chip delay. Furthermore, delay improvement at the full-chip level can be traded off to gain power reduction at the full-chip level. Finally, our experiments suggest that a sufficiently low supply voltage (= 0.4 V out of [0.2 and 0.8 V] range in our study) is needed to maximize power and performance gain at full-chip level.

Original languageEnglish
Pages (from-to)371-376
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume67
Issue number1
DOIs
Publication statusPublished - Jan 2020
Externally publishedYes

Fingerprint Dive into the research topics of 'Optimal ferroelectric parameters for negative capacitance field-effect transistors based on full-chip implementations-part II: scaling of the supply voltage'. Together they form a unique fingerprint.

Cite this