Abstract
This work is a significant stage of the project, "Digital Arithmetic Public-Key Cryptography". It constructs a modular multiplier for use in the channel of a Residue Number System (RNS). The modular multiplier is implemented on FPGA and optimized by evaluating different versions of the Improved Barrett Algorithm. The resulting optimized multiplier is 12 bits wide and uses separated multiplication and reduction.
Original language | English |
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Title of host publication | 2010 International Conference on Computational Intelligence and Software Engineering, CiSE 2010 |
Place of Publication | Piscataway, NJ |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Print) | 9781424453924 |
DOIs | |
Publication status | Published - 2010 |
Event | 2010 International Conference on Computational Intelligence and Software Engineering, CiSE 2010 - Wuhan, China Duration: 10 Dec 2010 → 12 Dec 2010 |
Other
Other | 2010 International Conference on Computational Intelligence and Software Engineering, CiSE 2010 |
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Country | China |
City | Wuhan |
Period | 10/12/10 → 12/12/10 |