Abstract
This work is a significant stage of the project, "Digital Arithmetic Public-Key Cryptography". It constructs a modular multiplier for use in the channel of a Residue Number System (RNS). The modular multiplier is implemented on FPGA and optimized by evaluating different versions of the Improved Barrett Algorithm. The resulting optimized multiplier is 12 bits wide and uses separated multiplication and reduction.
| Original language | English |
|---|---|
| Title of host publication | 2010 International Conference on Computational Intelligence and Software Engineering, CiSE 2010 |
| Place of Publication | Piscataway, NJ |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 1-4 |
| Number of pages | 4 |
| ISBN (Print) | 9781424453924 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2010 International Conference on Computational Intelligence and Software Engineering, CiSE 2010 - Wuhan, China Duration: 10 Dec 2010 → 12 Dec 2010 |
Other
| Other | 2010 International Conference on Computational Intelligence and Software Engineering, CiSE 2010 |
|---|---|
| Country/Territory | China |
| City | Wuhan |
| Period | 10/12/10 → 12/12/10 |
Bibliographical note
Copyright 2010 IEEE. Reprinted from 2010 International Conference on Computational Intelligence and Software Engineering (CiSE 2010) : December 10-12, 2010, Wuhan, China. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Macquarie University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.Fingerprint
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