Overlapped block-processing VLSI architecture for separable 2D filters

C. V. Niras*, Azadeh Safari, Yinan Kong

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

1 Citation (Scopus)

Abstract

Image and video processing applications require various 2D filters, many of them separable filters. This separable computation is an advantage since it implies less arithmetic computational complexity. But a direct hardware implementation of separable filter requires huge memory to store the results of the first 1D filter, which are not available in FPGAs or hard to implement in ASICs. Thus external memory access is required, which results in reduced speed due to the memory accessing overheads. This paper introduces an alternative approach with overlapped block processing, only requiring a memory size that is approximately equal to the image block size, thus no external memory access is required. As an example we implement the gradient calculation of the Sobel operator in a FPGA.

Original languageEnglish
Title of host publicationElectronics, Communications and Networks IV
Subtitle of host publicationProceedings of the 4th International Conference on Electronics, Communications and Networks, CECNet2014
EditorsAmir Hussain, Mirjana Ivanovic
Place of PublicationBoca Raton, FL
PublisherCRC Press/Balkema
Pages1355-1358
Number of pages4
ISBN (Electronic)9781315682105
ISBN (Print)9781138028302
Publication statusPublished - 2015
Event4th International Conference on Electronics, Communications and Networks, CECNet2014 - Beijing, China
Duration: 12 Dec 201415 Dec 2014

Other

Other4th International Conference on Electronics, Communications and Networks, CECNet2014
Country/TerritoryChina
CityBeijing
Period12/12/1415/12/14

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