Growing international interest in the development of space missions based on low-cost nano-/microsatellites demands new approaches to the design of reliable, low-cost, reconfigurable digital processing platforms. To meet these requirements, future systems will need to include application-specific processors to handle control-dominated tasks and hardware accelerators to cope with data- intensive workloads. Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs) provide an ideal platform for meeting these requirements with applicationspecific processors implemented as soft cores along with hardware accelerators on FPGA fabric. However, the main challenge to deploying reconfigurable systems in space is mitigating the impact of radiation-induced Single Event Upsets (SEUs). In considering the design of such heterogeneous systems, we present a survey of techniques commonly employed to guard against soft errors in application- specific processors that are conventionally targeted at ASICs and assess their suitability to FPGA implementation when partial reconfiguration is used to deal with SEUs in logic circuits. Finally, we report on the development of the RUSH payload, to be deployed on the UNSW-EC0 CubeSat due for launch in 2016, to test our design approach.
|Title of host publication||FPGAs and parallel architectures for aerospace applications|
|Subtitle of host publication||soft errors and fault-tolerant design|
|Editors||Fernanda Kastensmidt, Paolo Rech|
|Place of Publication||Cham, Switzerland|
|Publisher||Springer, Springer Nature|
|Number of pages||14|
|Publication status||Published - 1 Jan 2015|