Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digital-to-analog converter (HC-DAC). Unlike a regular DAC whose amplitude weights are defined by powers of two, an HC-DAC's amplitude weights are defined by a sine function. Thus, HC-DACs present intriguing design problems which cannot be solved using the conventional knowledge gathered from designing regular DACs. One such problem is managing the effect of mismatch between unit-elements in HC-DACs. This paper proposes a partial dynamic element matching (DEM) technique tailored for HC-DACs, which reduces the effect of mismatch, while preserving the power and area efficiency of DHSSs. The effectiveness of the DEM technique is evaluated using a DHSS circuit fabricated in an STMicroelectronics 130 nm CMOS technology. Test results show that applying the DEM technique increased the figure-of-merit of the DHSS by 40% at 2 MHz output frequency.
|Number of pages||14|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - Feb 2017|
- digital sinusoid signal generation
- harmonic rejection
- low harmonic distortion