Partial dynamic element matching technique for digital-to-analog converters used for digital harmonic-cancelling sine-wave synthesis

Pasindu Dissan Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)

Abstract

Digital harmonic-cancelling sine-wave synthesizers (DHSSs) use a 47 year old concept, recently revived as a power and area efficient solution for on-chip sine-wave synthesis. The operation of a DHSS involves amplitude scaling and summing a set of square-waves to produce a sampled sine-wave. The circuit which performs the scaling and summing operation is referred to as the harmonic-cancelling digital-to-analog converter (HC-DAC). Unlike a regular DAC whose amplitude weights are defined by powers of two, an HC-DAC's amplitude weights are defined by a sine function. Thus, HC-DACs present intriguing design problems which cannot be solved using the conventional knowledge gathered from designing regular DACs. One such problem is managing the effect of mismatch between unit-elements in HC-DACs. This paper proposes a partial dynamic element matching (DEM) technique tailored for HC-DACs, which reduces the effect of mismatch, while preserving the power and area efficiency of DHSSs. The effectiveness of the DEM technique is evaluated using a DHSS circuit fabricated in an STMicroelectronics 130 nm CMOS technology. Test results show that applying the DEM technique increased the figure-of-merit of the DHSS by 40% at 2 MHz output frequency.

Original languageEnglish
Pages (from-to)296-309
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume64
Issue number2
DOIs
Publication statusPublished - Feb 2017
Externally publishedYes

Keywords

  • DAC
  • DEM
  • digital sinusoid signal generation
  • harmonic rejection
  • low harmonic distortion

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