Performance analysis of digital phase locked loops with statistical filters for carrier synchronisation

Sithamparanathan Kandeepan*, Sam Reisenfeld

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

Abstract

The study of digital phase locked loops (DPLL) for carrier recovery exists for the past several years. A typical DPLL consists of a phase detector (PD), a numerically controlled oscillator (NCO), and a linear loop filter. Here we look into the design and analysis of DPLLs with statistical filters. In particular, we consider the median type of statistical filters incorporated within the loop. In this paper, the properties of the median type filters are first explored and followed by the design and performance analysis of the DPLL incorporating the median filter. Median filters in general have the tendency of rejecting statistical outliers and improving the jitter performance of the system. We consider two types of PD models for the analysis of the loop, first, the linear PD model, and second, the four quadrant arctan PD model. Probability density functions (pdf) are derived for the error signals within the loop by opening the loop assuming steady state conditions.

Original languageEnglish
Title of host publication2004 International Conference on Signal Processing and Communications, SPCOM
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages174-178
Number of pages5
ISBN (Print)0780386744, 9780780386747
Publication statusPublished - 2004
Externally publishedYes
Event2004 International Conference on Signal Processing and Communications, SPCOM - Bangalore, India
Duration: 11 Dec 200414 Dec 2004

Other

Other2004 International Conference on Signal Processing and Communications, SPCOM
CountryIndia
CityBangalore
Period11/12/0414/12/04

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