Performance analysis of radix-4 adders

Shahzad Asif*, Mark Vesterbacka

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4 circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a reduced number of transistors in the carry path is also investigated. Simulation results also confirm that the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-Bit ripple carry, 2-stage carry select, variable size carry select, and carry skip adders are implemented with the different full adders as building blocks. There are PDP savings, with one exception, for the 32-bit adders in the range 818% and EDP savings in the range 2153% using radix-4 as compared to radix-2.

Original languageEnglish
Pages (from-to)111-120
Number of pages10
JournalIntegration, the VLSI Journal
Volume45
Issue number2
DOIs
Publication statusPublished - Mar 2012

Keywords

  • Carry-based adder
  • CMOS full adder
  • Energy-delay product
  • Power-delay product
  • Radix-4 adder

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