Abstract
Multiplication is one of the most commonly used operations in the arithmetic. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. In the previous years the Booth encoding is widely used in the tree multipliers to increase the speed of the multiplier. However, the efficiency of the Booth encoders decreases with the technology scale down. In this paper we showed that the use of Booth encoders in fact increases the delay and power of the Wallace multiplier in the deep submicron technology. The radix-4 Booth-Wallace and the Wallace multipliers are implemented for various sizes and synthesized using Synopsys Design Compiler in 90nm process technology. The synthesis results show that the Wallace multiplier has up to 17% less delay and 70% less power consumption as compared to the radix-4 Booth-Wallace multipliers. The Power-Delay Product (PDP) of the Wallace multiplier is up to 68% lower than the Booth-Wallace multiplier.
| Original language | English |
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| Title of host publication | Proceedings of 2015 Electronic System Level Synthesis Conference, co-located with DAC, ESLsyn 2015 |
| Editors | Adam Morawiec, Sophie Cerisier |
| Place of Publication | Piscataway, NJ |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 17-22 |
| Number of pages | 6 |
| ISBN (Electronic) | 9791092279122 |
| Publication status | Published - 23 Dec 2015 |
| Event | 5th Electronic System Level Synthesis Conference, ESLsyn 2015 - San Francisco, United States Duration: 10 Jun 2015 → 11 Jun 2015 |
Other
| Other | 5th Electronic System Level Synthesis Conference, ESLsyn 2015 |
|---|---|
| Country/Territory | United States |
| City | San Francisco |
| Period | 10/06/15 → 11/06/15 |