Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling

Azadeh Safari*, Cheecottu Vayalil Niras, Yinan Kong

*Corresponding author for this work

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Digital image processing is widely used in fast and high-performance applications. The high speed and functional requirements of such applications, however, lead to increased power consumption. Hence, finding a way to solve the power-performance issues is of great importance. In this paper, we present the power-performance enhancement of a two-dimensional (2D) discrete wavelet transform (DWT) image processor using the residue number system (RNS) and the static voltage scaling (SVS) scheme. The aim of this paper is to investigate the effects of the RNS and SVS scheme on the proposed image processor. The original contributions of the proposed design include a low-complexity hardware architecture of the RNS-based filter banks, optimized transposition units and exploiting the SVS scheme to reduce the power consumption. The multiplierless scheme of the RNS-based filter banks and the binary-coded number format are used to save on hardware complexity, while modular arithmetics and 6-bit dyadic fraction filter coefficients are applied to improve the system performance. The bi-orthogonal discrete wavelet transform CDF97 is chosen to compress the images due to its multi-resolution features and its ability to localize finite signals. The proposed design has been synthesized using the generic library SAED90nmEDK with the Synopsys Design Compiler (DC).

Original languageEnglish
Pages (from-to)145-156
Number of pages12
JournalIntegration, the VLSI Journal
Volume53
DOIs
Publication statusPublished - Mar 2016

Keywords

  • High-speed arithmetic
  • Residue number system
  • Discrete wavelet transform
  • Low-power design
  • Image compression
  • Multi-voltage processor

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