TY - JOUR
T1 - Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling
AU - Safari, Azadeh
AU - Niras, Cheecottu Vayalil
AU - Kong, Yinan
PY - 2016/3
Y1 - 2016/3
N2 - Digital image processing is widely used in fast and high-performance applications. The high speed and functional requirements of such applications, however, lead to increased power consumption. Hence, finding a way to solve the power-performance issues is of great importance. In this paper, we present the power-performance enhancement of a two-dimensional (2D) discrete wavelet transform (DWT) image processor using the residue number system (RNS) and the static voltage scaling (SVS) scheme. The aim of this paper is to investigate the effects of the RNS and SVS scheme on the proposed image processor. The original contributions of the proposed design include a low-complexity hardware architecture of the RNS-based filter banks, optimized transposition units and exploiting the SVS scheme to reduce the power consumption. The multiplierless scheme of the RNS-based filter banks and the binary-coded number format are used to save on hardware complexity, while modular arithmetics and 6-bit dyadic fraction filter coefficients are applied to improve the system performance. The bi-orthogonal discrete wavelet transform CDF97 is chosen to compress the images due to its multi-resolution features and its ability to localize finite signals. The proposed design has been synthesized using the generic library SAED90nmEDK with the Synopsys Design Compiler (DC).
AB - Digital image processing is widely used in fast and high-performance applications. The high speed and functional requirements of such applications, however, lead to increased power consumption. Hence, finding a way to solve the power-performance issues is of great importance. In this paper, we present the power-performance enhancement of a two-dimensional (2D) discrete wavelet transform (DWT) image processor using the residue number system (RNS) and the static voltage scaling (SVS) scheme. The aim of this paper is to investigate the effects of the RNS and SVS scheme on the proposed image processor. The original contributions of the proposed design include a low-complexity hardware architecture of the RNS-based filter banks, optimized transposition units and exploiting the SVS scheme to reduce the power consumption. The multiplierless scheme of the RNS-based filter banks and the binary-coded number format are used to save on hardware complexity, while modular arithmetics and 6-bit dyadic fraction filter coefficients are applied to improve the system performance. The bi-orthogonal discrete wavelet transform CDF97 is chosen to compress the images due to its multi-resolution features and its ability to localize finite signals. The proposed design has been synthesized using the generic library SAED90nmEDK with the Synopsys Design Compiler (DC).
KW - High-speed arithmetic
KW - Residue number system
KW - Discrete wavelet transform
KW - Low-power design
KW - Image compression
KW - Multi-voltage processor
UR - http://www.scopus.com/inward/record.url?scp=84960114311&partnerID=8YFLogxK
U2 - 10.1016/j.vlsi.2015.12.006
DO - 10.1016/j.vlsi.2015.12.006
M3 - Article
AN - SCOPUS:84960114311
SN - 0167-9260
VL - 53
SP - 145
EP - 156
JO - Integration, the VLSI Journal
JF - Integration, the VLSI Journal
ER -