Raised source/drains for 50 nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy

A. M. Waite, N. S. Lloyd, K. Osman, W. Zhang, T. Ernst, H. Achard, Y. Wang, S. Deleonibus, P. L. F. Hemment, D. M. Bagnall, A. G. R. Evans, P. Ashburn*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


A selective epitaxy process for raised sources and drains is investigated, with growth performed at a pressure in the 1 Torr regime, rather than the more common CVD (10's of Torr) or UHV-CVD (1-40 mTorr) regimes. It is shown that selective growth can be achieved using a mixture of silane and dichlorosilane without any requirement for Cl2 or HCl in the gas stream. The selectivity of the process can be controlled by varying the silane: dichlorosilane ratio in the gas mixture, with a ratio between 1:1 and 3:1 giving selective growth. Facet-free selective epitaxy is achieved, the process is selective to silicon nitride and a growth activation energy of 2.4 eV is obtained. Raised source/drain MOSFET devices with channel lengths down to 50 nm have been fabricated and the thickness of the selective epitaxial silicon layer has been varied to investigate the effect of this parameter on device performance. Excellent sub-threshold characteristics are obtained and the sub-threshold slope, S, improves from 102 to 81.9 mV/dec as the raised source/drain thickness is increased from 50 nm to 100 nm. The raised source/drain also improves threshold voltage roll-off and drain induced barrier lowering. A decrease in both Ion and Ioff is seen with increasing RSD thickness, but the overall Ioff/Ion trade-off is unchanged.

Original languageEnglish
Pages (from-to)529-534
Number of pages6
JournalSolid-State Electronics
Issue number4
Publication statusPublished - Apr 2005
Externally publishedYes


  • raised source/drain
  • selective epitaxy
  • silicon epitaxy


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