Reconfigurable encryption system

Encrypt digital data

Md Jobayer Hossain, Md Billal Hossain, Khaled Mahbub Morshed

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

4 Citations (Scopus)

Abstract

This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user. All these methods are symmetric type block cipher cryptography. DES takes 64 bit key to encrypt each 64 bits block of the entire message. AES on the contrary takes 128 bit key to encrypt each 128 bits block. Providing reconfigurability, the architecture enables the user to choose one of the existing techniques according to the level of security required. So the designed architecture is both flexible and reliable enough for the user to secure their privacy of conversation or e-commerce transaction. The architecture is designed using Verilog hardware description language, synthesized in Xilinx Synthesis Tool (XST) and Simulated by Verilogger Pro 6.5. It may be implemented in commercially available FPGAs.

Original languageEnglish
Title of host publicationProceeding of the 15th International Conference on Computer and Information Technology, ICCIT 2012
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages429-435
Number of pages7
ISBN (Electronic)9781467348362
ISBN (Print)9781467348348, 9781467348331
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event15th International Conference on Computer and Information Technology, ICCIT 2012 - Chittagong, Bangladesh
Duration: 22 Dec 201224 Dec 2012

Other

Other15th International Conference on Computer and Information Technology, ICCIT 2012
CountryBangladesh
CityChittagong
Period22/12/1224/12/12

Keywords

  • 3 DES
  • AES
  • DES
  • Encryption
  • FPGA
  • RTL schematic
  • Symmetric key cryptography
  • timing diagram

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