Reconfigurable encryption system: Encrypt digital data

Md Jobayer Hossain; Md Billal Hossain; Khaled Mahbub Morshed

doi:10.1109/ICCITechn.2012.6509805

Reconfigurable encryption system: Encrypt digital data

Md Jobayer Hossain, Md Billal Hossain, Khaled Mahbub Morshed

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

5 Citations (Scopus)

Abstract

This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user. All these methods are symmetric type block cipher cryptography. DES takes 64 bit key to encrypt each 64 bits block of the entire message. AES on the contrary takes 128 bit key to encrypt each 128 bits block. Providing reconfigurability, the architecture enables the user to choose one of the existing techniques according to the level of security required. So the designed architecture is both flexible and reliable enough for the user to secure their privacy of conversation or e-commerce transaction. The architecture is designed using Verilog hardware description language, synthesized in Xilinx Synthesis Tool (XST) and Simulated by Verilogger Pro 6.5. It may be implemented in commercially available FPGAs.

Original language	English
Title of host publication	Proceeding of the 15th International Conference on Computer and Information Technology, ICCIT 2012
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	429-435
Number of pages	7
ISBN (Electronic)	9781467348362
ISBN (Print)	9781467348348, 9781467348331
DOIs	https://doi.org/10.1109/ICCITechn.2012.6509805
Publication status	Published - 2012
Externally published	Yes
Event	15th International Conference on Computer and Information Technology, ICCIT 2012 - Chittagong, Bangladesh Duration: 22 Dec 2012 → 24 Dec 2012

Other

Other	15th International Conference on Computer and Information Technology, ICCIT 2012
Country	Bangladesh
City	Chittagong
Period	22/12/12 → 24/12/12

Keywords

3 DES
AES
DES
Encryption
FPGA
RTL schematic
Symmetric key cryptography
timing diagram

Access to Document

10.1109/ICCITechn.2012.6509805

Link to publication in Scopus

Cite this

@inproceedings{df9ae31fe2d247899ccb44657d41676a,

title = "Reconfigurable encryption system: Encrypt digital data",

abstract = "This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user. All these methods are symmetric type block cipher cryptography. DES takes 64 bit key to encrypt each 64 bits block of the entire message. AES on the contrary takes 128 bit key to encrypt each 128 bits block. Providing reconfigurability, the architecture enables the user to choose one of the existing techniques according to the level of security required. So the designed architecture is both flexible and reliable enough for the user to secure their privacy of conversation or e-commerce transaction. The architecture is designed using Verilog hardware description language, synthesized in Xilinx Synthesis Tool (XST) and Simulated by Verilogger Pro 6.5. It may be implemented in commercially available FPGAs.",

keywords = "3 DES, AES, DES, Encryption, FPGA, RTL schematic, Symmetric key cryptography, timing diagram",

author = "Hossain, {Md Jobayer} and Hossain, {Md Billal} and Morshed, {Khaled Mahbub}",

year = "2012",

doi = "10.1109/ICCITechn.2012.6509805",

language = "English",

isbn = "9781467348348",

pages = "429--435",

booktitle = "Proceeding of the 15th International Conference on Computer and Information Technology, ICCIT 2012",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "15th International Conference on Computer and Information Technology, ICCIT 2012 ; Conference date: 22-12-2012 Through 24-12-2012",

}

Hossain, MJ, Hossain, MB & Morshed, KM 2012, Reconfigurable encryption system: Encrypt digital data. in Proceeding of the 15th International Conference on Computer and Information Technology, ICCIT 2012., 6509805, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 429-435, 15th International Conference on Computer and Information Technology, ICCIT 2012, Chittagong, Bangladesh, 22/12/12. https://doi.org/10.1109/ICCITechn.2012.6509805

Reconfigurable encryption system : Encrypt digital data. / Hossain, Md Jobayer; Hossain, Md Billal; Morshed, Khaled Mahbub.

Proceeding of the 15th International Conference on Computer and Information Technology, ICCIT 2012. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2012. p. 429-435 6509805.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

TY - GEN

T1 - Reconfigurable encryption system

T2 - 15th International Conference on Computer and Information Technology, ICCIT 2012

AU - Hossain, Md Jobayer

AU - Hossain, Md Billal

AU - Morshed, Khaled Mahbub

PY - 2012

Y1 - 2012

N2 - This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user. All these methods are symmetric type block cipher cryptography. DES takes 64 bit key to encrypt each 64 bits block of the entire message. AES on the contrary takes 128 bit key to encrypt each 128 bits block. Providing reconfigurability, the architecture enables the user to choose one of the existing techniques according to the level of security required. So the designed architecture is both flexible and reliable enough for the user to secure their privacy of conversation or e-commerce transaction. The architecture is designed using Verilog hardware description language, synthesized in Xilinx Synthesis Tool (XST) and Simulated by Verilogger Pro 6.5. It may be implemented in commercially available FPGAs.

AB - This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user. All these methods are symmetric type block cipher cryptography. DES takes 64 bit key to encrypt each 64 bits block of the entire message. AES on the contrary takes 128 bit key to encrypt each 128 bits block. Providing reconfigurability, the architecture enables the user to choose one of the existing techniques according to the level of security required. So the designed architecture is both flexible and reliable enough for the user to secure their privacy of conversation or e-commerce transaction. The architecture is designed using Verilog hardware description language, synthesized in Xilinx Synthesis Tool (XST) and Simulated by Verilogger Pro 6.5. It may be implemented in commercially available FPGAs.

KW - 3 DES

KW - AES

KW - DES

KW - Encryption

KW - FPGA

KW - RTL schematic

KW - Symmetric key cryptography

KW - timing diagram

UR - http://www.scopus.com/inward/record.url?scp=84878069855&partnerID=8YFLogxK

U2 - 10.1109/ICCITechn.2012.6509805

DO - 10.1109/ICCITechn.2012.6509805

M3 - Conference proceeding contribution

AN - SCOPUS:84878069855

SN - 9781467348348

SN - 9781467348331

SP - 429

EP - 435

BT - Proceeding of the 15th International Conference on Computer and Information Technology, ICCIT 2012

PB - Institute of Electrical and Electronics Engineers (IEEE)

CY - Piscataway, NJ

Y2 - 22 December 2012 through 24 December 2012

ER -

Reconfigurable encryption system: Encrypt digital data

Abstract

Other

Keywords

Access to Document

Fingerprint

Cite this