Reconfiguration network design for SEU recovery in FPGAs

Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

3 Citations (Scopus)

Abstract

Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however, are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we detail the design of a reconfiguration network that provides the infrastructure to enable SEU recovery in FPGAs. The reconfiguration network's structure and operation is detailed along with performance analysis using results from simulated and implemented designs. The results indicate that total error recovery time from SEUs is dominated by the reconfiguration delay, and that the communication delay of the reconfiguration network is relatively small.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Place of PublicationPiscataway, NJ
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1524-1527
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014
Externally publishedYes
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

Keywords

  • fault tolerance
  • radiation induced errors
  • reconfigurable hardware
  • reconfiguration network

Fingerprint

Dive into the research topics of 'Reconfiguration network design for SEU recovery in FPGAs'. Together they form a unique fingerprint.

Cite this