Reconfiguration network design for SEU recovery in FPGAs

Ediz Cetin; Oliver Diessel; Lingkan Gong; Victor Lai

doi:10.1109/ISCAS.2014.6865437

Reconfiguration network design for SEU recovery in FPGAs

Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

3 Citations (Scopus)

Abstract

Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however, are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we detail the design of a reconfiguration network that provides the infrastructure to enable SEU recovery in FPGAs. The reconfiguration network's structure and operation is detailed along with performance analysis using results from simulated and implemented designs. The results indicate that total error recovery time from SEUs is dominated by the reconfiguration delay, and that the communication delay of the reconfiguration network is relatively small.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Place of Publication	Piscataway, NJ
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1524-1527
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865437
Publication status	Published - 2014
Externally published	Yes
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 1 Jun 2014 → 5 Jun 2014

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	1/06/14 → 5/06/14

Keywords

fault tolerance
radiation induced errors
reconfigurable hardware
reconfiguration network

Access to Document

10.1109/ISCAS.2014.6865437

Cite this

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title = "Reconfiguration network design for SEU recovery in FPGAs",

abstract = "Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however, are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we detail the design of a reconfiguration network that provides the infrastructure to enable SEU recovery in FPGAs. The reconfiguration network's structure and operation is detailed along with performance analysis using results from simulated and implemented designs. The results indicate that total error recovery time from SEUs is dominated by the reconfiguration delay, and that the communication delay of the reconfiguration network is relatively small.",

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language = "English",

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booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",

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note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

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Cetin, E, Diessel, O, Gong, L & Lai, V 2014, Reconfiguration network design for SEU recovery in FPGAs. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, NJ, pp. 1524-1527, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865437

Reconfiguration network design for SEU recovery in FPGAs. / Cetin, Ediz; Diessel, Oliver; Gong, Lingkan; Lai, Victor.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE), 2014. p. 1524-1527.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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T1 - Reconfiguration network design for SEU recovery in FPGAs

AU - Cetin, Ediz

AU - Diessel, Oliver

AU - Gong, Lingkan

AU - Lai, Victor

PY - 2014

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N2 - Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however, are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we detail the design of a reconfiguration network that provides the infrastructure to enable SEU recovery in FPGAs. The reconfiguration network's structure and operation is detailed along with performance analysis using results from simulated and implemented designs. The results indicate that total error recovery time from SEUs is dominated by the reconfiguration delay, and that the communication delay of the reconfiguration network is relatively small.

AB - Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however, are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we detail the design of a reconfiguration network that provides the infrastructure to enable SEU recovery in FPGAs. The reconfiguration network's structure and operation is detailed along with performance analysis using results from simulated and implemented designs. The results indicate that total error recovery time from SEUs is dominated by the reconfiguration delay, and that the communication delay of the reconfiguration network is relatively small.

KW - fault tolerance

KW - radiation induced errors

KW - reconfigurable hardware

KW - reconfiguration network

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BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers (IEEE)

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Reconfiguration network design for SEU recovery in FPGAs

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