Reduction of substrate noise in sub clock frequency range

Syed Muhammad Yasser Sherazi, Shahzad Asif, Erik Backenius, Mark Vesterbacka

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.

Original languageEnglish
Article number5361350
Pages (from-to)1287-1297
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume57
Issue number6
DOIs
Publication statusPublished - 2010

Keywords

  • Flip-flops
  • Integrated circuit noise
  • Mixed analogdigital integrated circuits
  • Simultaneous switching noise
  • Substrate noise

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