Scalable thermal resistance model for single and multi-finger silicon-on-insulator MOSFETs

S. Khandelwal*, J. Watts, E. Tamilmani, L. Wagner

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

6 Citations (Scopus)

Abstract

This paper presents a thermal resistance model for silicon-on-insulator MOSFETs. The proposed model accounts for various heat dissipation paths in the device accurately and is accurate for both multi and single finger devices. Model development is based on carefully designed test structures to account for different heat dissipations paths. Improvement in the drain current fits across devices when using proposed model over standard BSIMSOI4.3 validates the model.

Original languageEnglish
Title of host publication2011 IEEE International Conference on Microelectronic Test Structures - 24th ICMTS Conference Proceedings
Place of PublicationPiscataway, New Jersey
Pages182-185
Number of pages4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event2011 24th IEEE International Conference on Microelectronic Test Structures, ICMTS 2011 - Amsterdam, Netherlands
Duration: 4 Apr 20117 Apr 2011

Other

Other2011 24th IEEE International Conference on Microelectronic Test Structures, ICMTS 2011
CountryNetherlands
CityAmsterdam
Period4/04/117/04/11

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