Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

3 Citations (Scopus)

Abstract

Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the reliability of an exemplar system is improved by up to 29% when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order or by up to 11% when the next component to be checked is chosen at run time based on the likelihood that it has failed.
Original languageEnglish
Title of host publication2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Subtitle of host publicationproceedings
Place of PublicationPiscataway, N.J., U.S.A
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1-4
Number of pages4
ISBN (Electronic)9781538603628
ISBN (Print)9781538603628
DOIs
Publication statusPublished - 2017
Event2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Cambridge, United Kingdom
Duration: 23 Oct 201725 Oct 2017

Conference

Conference2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
CountryUnited Kingdom
CityCambridge
Period23/10/1725/10/17

Keywords

  • Computational modeling
  • Field programmable gate arrays
  • Random access memory
  • Redundancy
  • Reliability engineering
  • Tunneling magnetoresistance

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