Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

Nguyen T. H. Nguyen; Ediz Cetin; Oliver Diessel

doi:10.1109/DFT.2017.8244455

Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

4 Citations (Scopus)

Abstract

Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the reliability of an exemplar system is improved by up to 29% when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order or by up to 11% when the next component to be checked is chosen at run time based on the likelihood that it has failed.

Original language	English
Title of host publication	2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Subtitle of host publication	proceedings
Place of Publication	Piscataway, N.J., U.S.A
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1-4
Number of pages	4
ISBN (Electronic)	9781538603628
ISBN (Print)	9781538603628
DOIs	https://doi.org/10.1109/DFT.2017.8244455
Publication status	Published - 2017
Event	2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Cambridge, United Kingdom Duration: 23 Oct 2017 → 25 Oct 2017

Conference

Conference	2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Country/Territory	United Kingdom
City	Cambridge
Period	23/10/17 → 25/10/17

Keywords

Computational modeling
Field programmable gate arrays
Random access memory
Redundancy
Reliability engineering
Tunneling magnetoresistance

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10.1109/DFT.2017.8244455

Cite this

Nguyen, N. T. H., Cetin, E., & Diessel, O. (2017). Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. In 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT): proceedings (pp. 1-4). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/DFT.2017.8244455

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title = "Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems",

abstract = "Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the reliability of an exemplar system is improved by up to 29% when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order or by up to 11% when the next component to be checked is chosen at run time based on the likelihood that it has failed.",

keywords = "Computational modeling, Field programmable gate arrays, Random access memory, Redundancy, Reliability engineering, Tunneling magnetoresistance",

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doi = "10.1109/DFT.2017.8244455",

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Nguyen, NTH, Cetin, E & Diessel, O 2017, Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT): proceedings. Institute of Electrical and Electronics Engineers (IEEE), Piscataway, N.J., U.S.A, pp. 1-4, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Cambridge, United Kingdom, 23/10/17. https://doi.org/10.1109/DFT.2017.8244455

Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. / Nguyen, Nguyen T. H.; Cetin, Ediz; Diessel, Oliver.
2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT): proceedings. Piscataway, N.J., U.S.A: Institute of Electrical and Electronics Engineers (IEEE), 2017. p. 1-4.

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

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AU - Cetin, Ediz

AU - Diessel, Oliver

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AB - Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the reliability of an exemplar system is improved by up to 29% when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order or by up to 11% when the next component to be checked is chosen at run time based on the likelihood that it has failed.

KW - Computational modeling

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Y2 - 23 October 2017 through 25 October 2017

ER -

Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems

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