TY - JOUR
T1 - Self-aligned gate-last process for quantum-well InAs transistor on insulator
AU - Cheng, Qi
AU - Wang, Zilun
AU - Shariar, Kazy
AU - Khandelwal, Sourabh
AU - Zeng, Yuping
PY - 2018/5/5
Y1 - 2018/5/5
N2 - This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.
AB - This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.
KW - III–V material
KW - MOSFET fabrication
KW - self-aligned process
KW - XOI transistor
UR - http://www.scopus.com/inward/record.url?scp=85041474318&partnerID=8YFLogxK
U2 - 10.1016/j.mee.2018.01.030
DO - 10.1016/j.mee.2018.01.030
M3 - Article
AN - SCOPUS:85041474318
SN - 0167-9317
VL - 191
SP - 42
EP - 47
JO - Microelectronic Engineering
JF - Microelectronic Engineering
ER -