Simulations of modular multipliers on FPGA

Yinan Kong*, Braden Phillips

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contributionpeer-review

Abstract

A diverse variety of algorithms and architectures for modular multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.

Original languageEnglish
Title of host publicationProceedings of the IASTED Asian Conference on Modelling and Simulation
EditorsL. Miao
Place of PublicationCalgary, Canada
PublisherACTA Press
Pages128-131
Number of pages4
ISBN (Print)9780889867017
Publication statusPublished - 2007
Externally publishedYes
EventIASTED Asian Conference on Modelling and Simulation - Beijing, China
Duration: 8 Oct 200710 Oct 2007

Other

OtherIASTED Asian Conference on Modelling and Simulation
CountryChina
CityBeijing
Period8/10/0710/10/07

Keywords

  • Cryptography
  • E-security
  • FPGA
  • Modular multiplication
  • Simulations

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