Simulations of modular multipliers on FPGA

Yinan Kong; Braden Phillips

Simulations of modular multipliers on FPGA

Yinan Kong^*, Braden Phillips

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference proceeding contribution › peer-review

Abstract

A diverse variety of algorithms and architectures for modular multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.

Original language	English
Title of host publication	Proceedings of the IASTED Asian Conference on Modelling and Simulation
Editors	L. Miao
Place of Publication	Calgary, Canada
Publisher	ACTA Press
Pages	128-131
Number of pages	4
ISBN (Print)	9780889867017
Publication status	Published - 2007
Externally published	Yes
Event	IASTED Asian Conference on Modelling and Simulation - Beijing, China Duration: 8 Oct 2007 → 10 Oct 2007

Other

Other	IASTED Asian Conference on Modelling and Simulation
Country/Territory	China
City	Beijing
Period	8/10/07 → 10/10/07

Keywords

Cryptography
E-security
FPGA
Modular multiplication
Simulations

Cite this

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title = "Simulations of modular multipliers on FPGA",

abstract = "A diverse variety of algorithms and architectures for modular multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.",

keywords = "Cryptography, E-security, FPGA, Modular multiplication, Simulations",

author = "Yinan Kong and Braden Phillips",

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booktitle = "Proceedings of the IASTED Asian Conference on Modelling and Simulation",

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note = "IASTED Asian Conference on Modelling and Simulation ; Conference date: 08-10-2007 Through 10-10-2007",

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AU - Kong, Yinan

AU - Phillips, Braden

PY - 2007

Y1 - 2007

N2 - A diverse variety of algorithms and architectures for modular multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.

AB - A diverse variety of algorithms and architectures for modular multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.

KW - Cryptography

KW - E-security

KW - FPGA

KW - Modular multiplication

KW - Simulations

UR - http://www.scopus.com/inward/record.url?scp=62649130171&partnerID=8YFLogxK

M3 - Conference proceeding contribution

AN - SCOPUS:62649130171

SN - 9780889867017

SP - 128

EP - 131

BT - Proceedings of the IASTED Asian Conference on Modelling and Simulation

A2 - Miao, L.

PB - ACTA Press

CY - Calgary, Canada

T2 - IASTED Asian Conference on Modelling and Simulation

Y2 - 8 October 2007 through 10 October 2007

ER -

Simulations of modular multipliers on FPGA

Abstract

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Keywords

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