Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation

Bruce Edwards*, Greg Efland, Neil Weste

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference proceeding contribution

Abstract

The authors describe features of the I-machine family, a third-generation symbolic processor architecture. The architecture is based on experience gained with the Symbolics 3600 and is targeted for a single-chip CMOS VLSI implementation.

Original languageEnglish
Title of host publicationIEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y.
Place of PublicationWashington, DC
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages502-505
Number of pages4
ISBN (Print)0818608021
Publication statusPublished - 1987
Externally publishedYes

Cite this

Edwards, B., Efland, G., & Weste, N. (1987). Symbolics I - machine architecture - a symbolic processor architecture for VLSI implementation. In IEEE International Conference on Computer Design, VLSI in computers & processors : ICCD '87, Rye Town Hilton, Rye Brook, N.Y. (pp. 502-505). Washington, DC: Institute of Electrical and Electronics Engineers (IEEE).